Study on sensing properties of tin oxide CO gas sensor with low power consumption

In this paper, the fabrication method of a new type of carbon monoxide gas sensor based on SnOx with low power consumption and its sensing characteristics have been reported. The electric conductance of this type of sensor evolves oscillation form regularly when the sensor is exposed to low level of CO gas. The oscillation amplitude is directly proportional to the concentration of CO gas over a wide range. The effects of relevant factors. such as. humidity, temperature and interference gases on the sensor properties were examined. The sensing oscillation response mechanism was also discussed.

Low power predictable memory and processing architectures

Great demand in power optimized devices shows promising economic potential and draws lots of attention in industry and research area. Due to the continuously shrinking CMOS process, not only dynamic power but also static power has emerged as a big concern in power reduction. Other than power optimization, average-case power estimation is quite significant for power budget allocation but also challenging in terms of time and effort. In this thesis, we will introduce a methodology to support modular quantitative analysis in order to estimate average power of circuits, on the basis of two concepts named Random Bag Preserving and Linear Compositionality. It can shorten simulation time and sustain high accuracy, resulting in increasing the feasibility of power estimation of big systems. For power saving, firstly, we take advantages of the low power characteristic of adiabatic logic and asynchronous logic to achieve ultra-low dynamic and static power. We will propose two memory cells, which could run in adiabatic and non-adiabatic mode. About 90% dynamic power can be saved in adiabatic mode when compared to other up-to-date designs. About 90% leakage power is saved. Secondly, a novel logic, named Asynchronous Charge Sharing Logic (ACSL), will be introduced. The realization of completion detection is simplified considerably. Not just the power reduction improvement, ACSL brings another promising feature in average power estimation called data-independency where this characteristic would make power estimation effortless and be meaningful for modular quantitative average case analysis. Finally, a new asynchronous Arithmetic Logic Unit (ALU) with a ripple carry adder implemented using the logically reversible/bidirectional characteristic exhibiting ultra-low power dissipation with sub-threshold region operating point will be presented. The proposed adder is able to operate multi-functionally.

Thermo-mechanical modelling of power electronics module structures

Power electronic modules distinguish themselves from other modules by their high power operation. These modules are used extensively in high power application markets such as aerospace, automotive, industrial and traction and drives. This paper discusses typical packaging technologies for power electronics modules. It also discusses the latest results from a UK research project investigating the physics-of-failure approach to reliability analysis and predictions for power modules. An integrated design enviroment for incorporating of affects of uncertainty into the design environment was outlined.

Reliability analysis for power electronics modules

This paper discusses the reliability of power electronics modules. The approach taken combines numerical modeling techniques with experimentation and accelerated testing to identify failure modes and mechanisms for the power module structure and most importantly the root cause of a potential failure. The paper details results for two types of failure (i) wire bond fatigue and (ii) substrate delamination. Finite element method modeling techniques have been used to predict the stress distribution within the module structures. A response surface optimisation approach has been employed to enable the optimal design and parameter sensitivity to be determined. The response surface is used by a Monte Carlo method to determine the effects of uncertainty in the design.

Lifetime prediction for power electronics module substrate mount-down solder interconnect

A numerical modeling method for the prediction of the lifetime of solder joints of relatively large solder area under cyclic thermal-mechanical loading conditions has been developed. The method is based on the Miner's linear damage accumulation rule and the properties of the accumulated plastic strain in front of the crack in large area solder joint. The nonlinear distribution of the damage indicator in the solder joints have been taken into account. The method has been used to calculate the lifetime of the solder interconnect in a power module under mixed cyclic loading conditions found in railway traction control applications. The results show that the solder thickness is a parameter that has a strong influence on the damage and therefore the lifetime of the solder joint while the substrate width and the thickness of the baseplate are much less important for the lifetime

Optimizing the reliability of power electronics module isolation substrates

Optimal design of a power electronics module isolation substrate is assessed using a combination of finite element structural mechanics analysis and response surface optimisation technique. Primary failure modes in power electronics modules include the loss of structural integrity in the ceramic substrate materials due to stresses induced through thermal cycling. Analysis of the influence of ceramic substrate design parameters is undertaken using a design of experiments approach. Finite element analysis is used to determine the stress distribution for each design, and the results are used to construct a quadratic response surface function. A particle swarm optimisation algorithm is then used to determine the optimal substrate design. Analysis of response surface function gradients is used to perform sensitivity analysis and develop isolation substrate design rules. The influence of design uncertainties introduced through manufacturing tolerances is assessed using a Monte-Carlo algorithm, resulting in a stress distribution histogram. The probability of failure caused by the violation of design constraints has been analyzed. Six geometric design parameters are considered in this work and the most important design parameters have been identified. Overall analysis results can be used to enhance the design and reliability of the component.

A prognostic assessment method for power electronics modules

This paper describes a prognostic method which combines the physics of failure models with probability reasoning algorithm. The measured real time data (temperature vs. time) was used as the loading profile for the PoF simulations. The response surface equation of the accumulated plastic strain in the solder interconnect in terms of two variables (average temperature, and temperature amplitude) was constructed. This response surface equation was incorporated into the lifetime model of solder interconnect, and therefore the remaining life time of the solder component under current loading condition was predicted. The predictions from PoF models were also used to calculate the conditional probability table for a Bayesian Network, which was used to take into account of the impacts of the health observations of each product in lifetime prediction. The prognostic prediction in the end was expressed as the probability for the product to survive the expected future usage. As a demonstration, this method was applied to an IGBT power module used for aircraft applications.

Computer simulation of crack propagation in power electronics module solder joints

A numerical modelling method for the analysis of solder joint damage and crack propagation has been described in this paper. The method is based on the disturbed state concept. Under cyclic thermal-mechanical loading conditions, the level of damage that occurs in solder joints is assumed to be a simple monotonic scalar function of the accumulated equivalent plastic strain. The increase of damage leads to crack initiation and propagation. By tracking the evolution of the damage level in solder joints, crack propagation path and rate can be simulated using Finite Element Analysis method. The discussions are focused on issues in the implementation of the method. The technique of speeding up the simulation and the mesh dependency issues are analysed. As an example of the application of this method, crack propagation in solder joints of power electronics modules under cyclic thermal-mechanical loading conditions has been analyzed and the predicted cracked area size after 3000 loading cycles is consistent with experimental results.

Computer simulation of aluminium wirebonds with globtop in power electronics modules

In this paper, computer modelling techniques are used to analyse the effects of globtops on the reliability of aluminium wirebonds in power electronics modules under cyclic thermal-mechanical loading conditions. The sensitivity of the wirehond reliability to the changes of the geometric and the material property parameters of wirebond globtop are evaluated and the optimal combination of the Young's modulus and the coefficient of thermal expansion have been predicted.

Modelling of jet-impingement cooling for power electronics

The use of an innovative jet impingement cooling system in a power electronics application is investigated using numerical analysis. The jet impingement system, outlined by Skuriat et al, consists of a series of cells each containing an array of holes. Cooling fluid is forced through the device, forming an array of impingement jets. The jets are arranged in a manner, which induces a high degree of mixing in the interface boundary layer. This increase in turbulent mixing is intended to induce higher Nusselt numbers and effective heat transfer coefficients. Enhanced cooling efficiency enables the power electronics module to operate at a lower temperature, greatly enhancing long-term reliability. The results obtained through numerical modelling deviates markedly from the experimentally derived data. The disparity is most likely due to the turbulence model selected and further analysis is required, involving evaluation of more advanced turbulence models.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.