Indoor location using fingerprinting and fuzzy logic

Indoor location systems cannot rely on technologies such as GPS (Global Positioning System) to determine the position of a mobile terminal, because its signals are blocked by obstacles such as walls, ceilings, roofs, etc. In such environments. The use of alternative techniques, such as the use of wireless networks, should be considered. The location estimation is made by measuring and analysing one of the parameters of the wireless signal, usually the received power. One of the techniques used to estimate the locations using wireless networks is fingerprinting. This technique comprises two phases: in the first phase data is collected from the scenario and stored in a database; the second phase consists in determining the location of the mobile node by comparing the data collected from the wireless transceiver with the data previously stored in the database. In this paper an approach for localisation using fingerprinting based on Fuzzy Logic and pattern searching is presented. The performance of the proposed approach is compared with the performance of classic methods, and it presents an improvement between 10.24% and 49.43%, depending on the mobile node and the Fuzzy Logic parameters.ł

Logic functions based on optical bias controlled SIC Tandem devices

The purpose of this paper is the design of an optoelectronic circuit based on a-SiC technology, able to act simultaneously as a 4-bit binary encoder or a binary decoder in a 4-to-16 line configurations and show multiplexer-based logical functions. The device consists of a p-i'(a-SiC:H)-n/p-i(a-Si:H)-n multilayered structure produced by PECVD. To analyze it under information-modulated wave (color channels) and uniform irradiation (background) four monochromatic pulsed lights (input channels): red, green, blue and violet shine on the device. Steady state optical bias was superimposed separately from the front and the back sides, and the generated photocurrent was measured. Results show that the devices, under appropriate optical bias, act as reconfigurable active filters that allow optical switching and optoelectronic logic functions development providing the possibility for selective removal of useless wavelengths. The logic functions needed to construct any other complex logic functions are the NOT, and both or either an AND or an OR. Any other complex logic function that might be found can also be used as building blocks to achieve the functions needed for the retrieval of channels within the WDM communication link. (C) 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Water treatments in semi-closed cooling circuits and their impact on the quality of effluents discharged by CERN

Dissertação apresentada à Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia do Ambiente, Gestão de Sistemas Ambientais

Water treatments in semi-closed cooling circuits and their impact on the quality of effluents discharged by CERN

Mestrado integrado em Engenharia do Ambiente, perfil: Gestão de Sistemas Ambientais

A Logic and tool for local reasoning about security protocols

Trabalho apresentado no âmbito do Mestrado em Engenharia Informática, como requisito parcial para obtenção do grau de Mestre em Engenharia Informática

Automated design of microwave discrete tuning differential capacitance circuits in Si-integrated technologies

A genetic algorithm used to design radio-frequency binary-weighted differential switched capacitor arrays (RFDSCAs) is presented in this article. The algorithm provides a set of circuits all having the same maximum performance. This article also describes the design, implementation, and measurements results of a 0.25 lm BiCMOS 3-bit RFDSCA. The experimental results show that the circuit presents the expected performance up to 40 GHz. The similarity between the evolutionary solutions, circuit simulations, and measured results indicates that the genetic synthesis method is a very useful tool for designing optimum performance RFDSCAs.

Light-activated amplification in SiC Tandem devices: A capacitive active filter model

Characteristics of tunable wavelength pi'n/pin filters based on a-SiC:H multilayered stacked cells are studied both experimentally and theoretically. Results show that the device combines the demultiplexing operation with the simultaneous photodetection and self amplification of the signal. An algorithm to decode the multiplex signal is established. A capacitive active band-pass filter model is presented and supported by an electrical simulation of the state variable filter circuit. Experimental and simulated results show that the device acts as a state variable filter. It combines the properties of active high-pass and low-pass filter sections into a capacitive active band-pass filter using a changing capacitance to control the power delivered to the load.

Automated synthesis procedure of RF discrete tuning differential capacitance circuits

The paper presents a RFDSCA automated synthesis procedure. This algorithm determines several RFDSCA circuits from the top-level system specifications all with the same maximum performance. The genetic synthesis tool optimizes a fitness function proportional to the RFDSCA quality factor and uses the epsiv-concept and maximin sorting scheme to achieve a set of solutions well distributed along a non-dominated front. To confirm the results of the algorithm, three RFDSCAs were simulated in SpectreRF and one of them was implemented and tested. The design used a 0.25 mum BiCMOS process. All the results (synthesized, simulated and measured) are very close, which indicate that the genetic synthesis method is a very useful tool to design optimum performance RFDSCAs.

A fractional calculus perspective in the evolutionary design of combinational circuits

This paper analyses the performance of a genetic algorithm (GA) in the synthesis of digital circuits using two novel approaches. The first concept consists in improving the static fitness function by including a discontinuity evaluation. The measure of variability in the error of the Boolean table has similarities with the function continuity issue in classical calculus. The second concept extends the static fitness by introducing a fractional-order dynamical evaluation.

Novel techniques for the design and practical realization of switched-capacitor circuits in deep-submicron CMOS technologies

Dissertação apresentada para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores pela Universidade Nova de Lisboa, Faculdade de Ciências e Tecnologia

Low-voltage low-power CMOS analogue circuits for Gaussian and uniform noise generation

IEEE International Symposium on Circuits and Systems, MAY 25-28, 2003, Bangkok, Thailand. (ISI Web of Science)

A framework for self-healing radiation-tolerant implementations on reconfigurable FPGAs

To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant implementations, based on triple modular redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like the effects of multi-bit upsets (MBU) or fault accumulation, have also to be addressed. Furthermore, in case of a fault occurrence the correct operation of the affected module must be restored and the current state of the circuit coherently re-established. A solution that enables the autonomous correct restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in realtime, while keeping the normal operation of the circuit, is presented in this paper.

A framework for fault tolerant real time systems based on reconfigurable FPGAs

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

Digitally programmable delay-locked-loop with adaptive charge pump current for UWB radar system

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para obtenção do grau de Mestre em Engenharia Electrotécnica e Computadores