ICEPOLE: High-speed, hardware-oriented authenticated encryption

This paper introduces our dedicated authenticated encryption scheme ICEPOLE. ICEPOLE is a high-speed hardware-oriented scheme, suitable for high-throughput network nodes or generally any environment where specialized hardware (such as FPGAs or ASICs) can be used to provide high data processing rates. ICEPOLE-128 (the primary ICEPOLE variant) is very fast. On the modern FPGA device Virtex 6, a basic iterative architecture of ICEPOLE reaches 41 Gbits/s, which is over 10 times faster than the equivalent implementation of AES-128-GCM. The throughput-to-area ratio is also substantially better when compared to AES-128-GCM. We have carefully examined the security of the algorithm through a range of cryptanalytic techniques and our findings indicate that ICEPOLE offers high security level.

A Hardware Grid Simulator to Test Grid-Connected Inverter Systems.

Grid-connected systems when put to use at the site would experience scenarios like voltage sag, voltage swell, frequency deviations and unbalance which are common in the real world grid. When these systems are tested at laboratory, these scenarios do not exist and an almost stiff voltage source is what is usually seen. But, to qualify the grid-connected systems to operate at the site, it becomes essential to test them under the grid conditions mentioned earlier. The grid simulator is a hardware that can be programmed to generate some of the typical conditions experienced by the grid-connected systems at site. It is an inverter that is controlled to act like a voltage source in series with a grid impedance. The series grid impedance is emulated virtually within the inverter control rather than through physical components, thus avoiding the losses and the need for bulky reactive components. This paper describes the design of a grid simulator. Control implementation issues are highlighted in the experimental results.

Lenient Execution and Concurrent Execution of Re-entrant Routines: Efficient Implementation in Data Flow Systems

Implementation details of efficient schemes for lenient execution and concurrent execution of re-entrant routines in a data flow model have been discussed in this paper. The proposed schemes require no extra hardware support and utilise the existing hardware resources such as the Matching Unit and Memory Network Interface, effectively to achieve the above mentioned goals.

Design and implementation of a PC-based FPGA tester

A new range of programmable logic devices are revolutionizing the way complex digital hardware is designed and built all over the world. Being able to test these devices in order to validate and dynamically improve on the design is crucial. This paper describes a low-cost FPGA tester that can test SRAM based FPGAs in the laboratory.

Adaptive Filtering Technique and DSP Based Implementation for High-Speed Distance Protection

The paper presents an adaptive Fourier filtering technique and a relaying scheme based on a combination of a digital band-pass filter along with a three-sample algorithm, for applications in high-speed numerical distance protection. To enhance the performance of above-mentioned technique, a high-speed fault detector has been used. MATLAB based simulation studies show that the adaptive Fourier filtering technique provides fast tripping for near faults and security for farther faults. The digital relaying scheme based on a combination of digital band-pass filter along with three-sample data window algorithm also provides accurate and high-speed detection of faults. The paper also proposes a high performance 16-bit fixed point DSP (Texas Instruments TMS320LF2407A) processor based hardware scheme suitable for implementation of the above techniques. To evaluate the performance of the proposed relaying scheme under steady state and transient conditions, PC based menu driven relay test procedures are developed using National Instruments LabVIEW software. The test signals are generated in real time using LabVIEW compatible analog output modules. The results obtained from the simulation studies as well as hardware implementations are also presented.

VLSI Implementation of Spatial prediction Based Image Compression Scheme

We propose the design and implementation of hardware architecture for spatial prediction based image compression scheme, which consists of prediction phase and quantization phase. In prediction phase, the hierarchical tree structure obtained from the test image is used to predict every central pixel of an image by its four neighboring pixels. The prediction scheme generates an error image, to which the wavelet/sub-band coding algorithm can be applied to obtain efficient compression. The software model is tested for its performance in terms of entropy, standard deviation. The memory and silicon area constraints play a vital role in the realization of the hardware for hand-held devices. The hardware architecture is constructed for the proposed scheme, which involves the aspects of parallelism in instructions and data. The processor consists of pipelined functional units to obtain the maximum throughput and higher speed of operation. The hardware model is analyzed for performance in terms throughput, speed and power. The results of hardware model indicate that the proposed architecture is suitable for power constrained implementations with higher data rate

Speed and Area Optimized Implementation of H.264 8X8 DCT Transform and Quantizer

H.264 is a video codec standard which delivers high resolution video even at low bit rates. To provide high throughput at low bit rates hardware implementations are essential. In this paper, we propose hardware implementations for speed and area optimized DCT and quantizer modules. To target above criteria we propose two architectures. First architecture is speed optimized which gives a high throughput and can meet requirements of 4096x2304 frame at 30 frames/sec. Second architecture is area optimized and occupies 2009 LUTs in Altera’s stratix-II and can meet the requirements of 1080HD at 30 frames/sec.

Derating Based Hardware Optimizations in Soft Error Tolerant Designs

Ensuring reliable operation over an extended period of time is one of the biggest challenges facing present day electronic systems. The increased vulnerability of the components to atmospheric particle strikes poses a big threat in attaining the reliability required for various mission critical applications. Various soft error mitigation methodologies exist to address this reliability challenge. A general solution to this problem is to arrive at a soft error mitigation methodology with an acceptable implementation overhead and error tolerance level. This implementation overhead can then be reduced by taking advantage of various derating effects like logical derating, electrical derating and timing window derating, and/or making use of application redundancy, e. g. redundancy in firmware/software executing on the so designed robust hardware. In this paper, we analyze the impact of various derating factors and show how they can be profitably employed to reduce the hardware overhead to implement a given level of soft error robustness. This analysis is performed on a set of benchmark circuits using the delayed capture methodology. Experimental results show upto 23% reduction in the hardware overhead when considering individual and combined derating factors.

Foot-mounted INS for everybody - an open-source embedded implementation

We present an open-source, realtime, embedded implementation of a foot-mounted, zero-velocity-update-aided inertial navigation system. The implementation includes both hardware design and software, uses off-the-shelf components and assembly methods, and features a standard USB interface. The software is written in C and can easily be modified to run user implemented algorithms. The hardware design and the software are released under permissive open-source licenses and production files, source code, documentation, and further resources are available at www.openshoe.org. The reproduction cost for a single unit is below $800, with the inertial measurement unit making up the bulk ($700). The form factor of the implementation is small enough for it to be integrated in the sole of a shoe. A performance evaluation of the system shows a position errors for short trajectories (<;100 [m]) of ± 0.2-1% of the traveled distance, depending on the shape of trajectory.

Soft Real Time Implementation of a Cognitive Radio Testbed for Frequency Hopping Primary Satisfying QoS Requirements

The Cognitive Radio (CR) is a promising technology which provides a novel way to subjugate the issue of spectrum underutilization caused due to the fixed spectrum assignment policies. In this paper we report the design and implementation of a soft-real time CR MAC, consisting of multiple secondary users, in a frequency hopping (Fit) primary scenario. This MAC is capable of sensing the spectrum and dynamically allocating the available frequency bands to multiple CR users based on their QoS requirements. As the primary is continuously hopping, a method has also been implemented to detect the hop instant of the primary network. Synchronization usually requires real time support, however we have been able to achieve this with a soft-real time technique which enables a fully software implementation of CR MAC layer. We demonstrate the wireless transmission and reception of video over this CR testbed through opportunistic spectrum access. The experiments carried out use an open source software defined radio package called GNU Radio and a basic radio hardware component USRP.

ANRC Hybrid Test Bed Implementation and an End-to-End Performance Characterization of Dynamic Spectrum Access

An abundance of spectrum access and sensing algorithms are available in the dynamic spectrum access (DSA) and cognitive radio (CR) literature. Often, however, the functionality and performance of such algorithms are validated against theoretical calculations using only simulations. Both the theoretical calculations and simulations come with their attendant sets of assumptions. For instance, designers of dynamic spectrum access algorithms often take spectrum sensing and rendezvous mechanisms between transmitter-receiver pairs for granted. Test bed designers, on the other hand, either customize so much of their design that it becomes difficult to replicate using commercial off the shelf (COTS) components or restrict themselves to simulation, emulation /hardware-in-Ioop (HIL), or pure hardware but not all three. Implementation studies on test beds sophisticated enough to combine the three aforementioned aspects, but at the same time can also be put together using COTS hardware and software packages are rare. In this paper we describe i) the implementation of a hybrid test bed using a previously proposed hardware agnostic system architecture ii) the implementation of DSA on this test bed, and iii) the realistic hardware and software-constrained performance of DSA. Snapshot energy detector (ED) and Cumulative Summation (CUSUM), a sequential change detection algorithm, are available for spectrum sensing and a two-way handshake mechanism in a dedicated control channel facilitates transmitter-receiver rendezvous.

Design and implementation of spectrum sensing for cognitive radios with a frequency-hopping primary system

In this work, spectrum sensing for cognitive radios is considered in the presence of multiple Primary Users (PU) using frequency-hopping communication over a set of frequency bands. The detection performance of the Fast Fourier Transform (FFT) Average Ratio (FAR) algorithm is obtained in closed-form, for a given FFT size and number of PUs. The effective throughput of the Secondary Users (SU) is formulated as an optimization problem with a constraint on the maximum allowable interference on the primary network. Given the hopping period of the PUs, the sensing duration that maximizes the SU throughput is derived. The results are validated using Monte Carlo simulations. Further, an implementation of the FAR algorithm on the Lyrtech (now, Nutaq) small form factor software defined radio development platform is presented, and the performance recorded through the hardware is observed to corroborate well with that obtained through simulations, allowing for implementation losses. (C) 2015 Elsevier B.V. All rights reserved.

Implementación hardware de un robot humanoide.

[ES]Este trabajo describe una serie de mejoras aplicables a un kit comercial de robot humanoide Robonova, con el fin de que este reproduzca el comportamiento cinemático del ser humano con mayor autonomía. Entre ellas destacan la implementación de sensores infrarrojos, sensores de posición, cámaras de visión y conexiones en serie de servomotores. Todo ello controlado desde un ordenador de placa reducida Raspberry Pi.

Hardware reconfigurável para identificação de radionuclídeos utilizando o método de agrupamento subtrativo.

Fontes radioativas possuem radionuclídeos. Um radionuclídeo é um átomo com um núcleo instável, ou seja, um núcleo caracterizado pelo excesso de energia que está disponível para ser emitida. Neste processo, o radionuclídeo sofre o decaimento radioativo e emite raios gama e partículas subatômicas, constituindo-se na radiação ionizante. Então, a radioatividade é a emissão espontânea de energia a partir de átomos instáveis. A identificação correta de radionuclídeos pode ser crucial para o planejamento de medidas de proteção, especialmente em situações de emergência, definindo o tipo de fonte de radiação e seu perigo radiológico. Esta dissertação apresenta a aplicação do método de agrupamento subtrativo, implementada em hardware, para um sistema de identificação de elementos radioativos com uma resposta rápida e eficiente. Quando implementados em software, os algoritmos de agrupamento consumem muito tempo de processamento. Assim, uma implementação dedicada para hardware reconfigurável é uma boa opção em sistemas embarcados, que requerem execução em tempo real, bem como baixo consumo de energia. A arquitetura proposta para o hardware de cálculo do agrupamento subtrativo é escalável, permitindo a inclusão de mais unidades de agrupamento subtrativo para operarem em paralelo. Isso proporciona maior flexibilidade para acelerar o processo de acordo com as restrições de tempo e de área. Os resultados mostram que o centro do agrupamento pode ser identificado com uma boa eficiência. A identificação desses pontos pode classificar os elementos radioativos presentes em uma amostra. Utilizando este hardware foi possível identificar mais do que um centro de agrupamento, o que permite reconhecer mais de um radionuclídeo em fontes radioativas. Estes resultados revelam que o hardware proposto pode ser usado para desenvolver um sistema portátil para identificação radionuclídeos.

Implementation of semi-active damping on a tri-axle heavy-vehicle suspension

A semi-active truck damper was developed in conjunction with a commercial shock absorber manufacturer. A linearized damper model was developed for control system design purposes. Open- and closed-loop damper force tracking control was implemented, with tests showing that an open-loop approach gave the best compromise between response speed and accuracy. A hardware-in-the-loop test facility was used to investigate performance of the damper when combined with a simulated quarter-car model. The input to the vehicle model was a set of randomly generated road profiles, each profile traversed at an appropriate speed. Modified skyhook damping tests showed a simultaneous improvement over the optimum passive case of 13 per cent in vertical body acceleration and 8 per cent in dynamic tyre forces. Full-scale vehicle tests of the damper on a heavy tri-axle trailer were carried out. Implementation of modified skyhook damping yielded a simultaneous improvement over the optimum passive case of 8 per cent in vertical body acceleration and 8 per cent in dynamic tyre forces. © IMechE 2008.