Taste components of Sherry wines

Sherry wine has characteristic taste and aroma, different from other wine-based alcoholic beverages. This paper reports a study of the non-volatile, low-molecular weight compounds found in sherry and related alcoholic beverages that may contribute to taste. Compounds analysed included free amino acids, organic acids, sugars and small peptides (linear and cyclic). A series of seven diketopiperazines (cyclic dipeptides) namely, cyclo(Leu-Leu), cyclo(Pro-Leu), cyclo(Pro-Ile), cyclo(Pro-Met), cyclo( Pro-Val), cyclo(Pro-Pro) and cyclo(Val-Ala) were identified for the first time in sherry. Although traces were found in some other alcoholic beverages, levels were low compared with sherry. The base wine used in the sherry production had only traces of diketopiperazines, indicating that the casking stage of sherry production might be responsible for their formation.

The use of spray drying technology to reduce bitter taste of casein hydrolysate

The utilization of protein hydrolysates in food systems is frequently hindered due to their bitterness and hygroscopicity. Spray drying technology could be an alternative for reducing these problems. The aim of this work was to reduce or to mask the casein hydrolysate bitter taste using spray drying and mixtures of gelatin and soy protein isolate (SPI) as carriers. Six formulations were studied: three with 20% of hydrolysate and 80% of mixture (gelatine/SPI at proportions of 50/50, 40/60 and 60/40%) and three with 30% of hydrolysate and 70% of mixture (gelatine/SPI at proportions of 50/50, 40/60 and 60/40%). The spray-dried formulations were evaluated by SEM, hygroscopicity, thermal behavior (DSC), dissolution, and bitter taste, by a trained sensory panel using a paired-comparison test (free samples vs. spray-dried samples); all samples were presented in powder form. SEM analysis showed mostly spherically shaped particles, with many concavities and some particles with pores. All formulations were oil and water compatible and showed lower hygroscopicity values than free casein hydrolysate. At Aw 0.83, the free hydrolysate showed Tg about 25 degrees C lower than the formulations, indicating that the formulations may be more stable at Aw >= 0.65 since the glass transition should be prevented. The sensory panel found the formulations, tasted in the powder form, to be less bitter (P < 0.05) than the free casein hydrolysate. These results indicated that spray drying of casein hydrolysate with mixtures of gelatin and SPI was successful to attenuate the bitterness of casein hydrolysate. Thus, spray drying widens the possibilities of application of casein hydrolysates. (C) 2009 Elsevier Ltd. All rights reserved.

Nutrient Selection in the Absence of Taste Receptor Signaling

When allowed to choose between different macronutrients, most animals display a strong attraction toward carbohydrates compared with proteins. It remains uncertain, however, whether this food selection pattern depends primarily on the sensory properties intrinsic to each nutrient or, alternatively, metabolic signals can act independently of the hedonic value of sweetness to stimulate elevated sugar intake. Here we show that Trpm5(-/-) mice, which lack the cellular mechanisms required for sweet and several forms of L-amino acid taste transduction, develop a robust preference for D-glucose compared with isocaloric L-serine independently of the perception of sweetness. Moreover, a close relationship was found between glucose oxidation and taste-independent nutrient intake levels, with animals increasing intake as a function of glucose oxidation rates. Furthermore, microdialysis measurements revealed nutrient-specific dopaminergic responses in accumbens and dorsal striatum during intragastric infusions of glucose or serine. Specifically, intragastric infusions of glucose induced significantly higher levels of dopamine release compared with isocaloric serine in both ventral and dorsal striatum. Intragastric stimulation of dopamine release seemed to depend on glucose utilization, because administration of an anti-metabolic glucose analog resulted in lower dopamine levels in striatum, an effect that was reversed by intravenous glucose infusions. Together, our findings suggest that carbohydrate-specific preferences can develop independently of taste quality or caloric load, an effect associated with the ability of a given nutrient to regulate glucose metabolism and stimulate brain dopamine centers.

Redes-em-Chip : arquiteturas e modelos para avaliação de área e desempenho

Com o advento dos processos submicrônicos, a capacidade de integração de transistores tem atingido níveis que possibilitam a construção de um sistema completo em uma única pastilha de silício. Esses sistemas, denominados sistemas integrados, baseiam-se no reuso de blocos previamente projetados e verificados, os quais são chamados de núcleos ou blocos de propriedade intelectual. Os sistemas integrados atuais incluem algumas poucas dezenas de núcleos, os quais são interconectados por meio de arquiteturas de comunicação baseadas em estruturas dedicadas de canais ponto-a-ponto ou em estruturas reutilizáveis constituídas por canais multiponto, denominadas barramentos. Os futuros sistemas integrados irão incluir de dezenas a centenas de núcleos em um mesmo chip com até alguns bilhões de transistores, sendo que, para atender às pressões do mercado e amortizar os custos de projeto entre vários sistemas, é importante que todos os seus componentes sejam reutilizáveis, incluindo a arquitetura de comunicação. Das arquiteturas utilizadas atualmente, o barramento é a única que oferece reusabilidade. Porém, o seu desempenho em comunicação e o seu consumo de energia degradam com o crescimento do sistema. Para atender aos requisitos dos futuros sistemas integrados, uma nova alternativa de arquitetura de comunicação tem sido proposta na comunidade acadêmica. Essa arquitetura, denominada rede-em-chip, baseia-se nos conceitos utilizados nas redes de interconexão para computadores paralelos. Esta tese se situa nesse contexto e apresenta uma arquitetura de rede-em-chip e um conjunto de modelos para a avaliação de área e desempenho de arquiteturas de comunicação para sistemas integrados. A arquitetura apresentada é denominada SoCIN (System-on-Chip Interconnection Network) e apresenta como diferencial o fato de poder ser dimensionada de modo a atender a requisitos de custo e desempenho da aplicação alvo. Os modelos desenvolvidos permitem a estimativa em alto nível da área em silício e do desempenho de arquiteturas de comunicação do tipo barramento e rede-em-chip. São apresentados resultados que demonstram a efetividade das redes-em-chip e indicam as condições que definem a aplicabilidade das mesmas.

Reuse-based test planning for core-based systems-on-chip

Electronic applications are currently developed under the reuse-based paradigm. This design methodology presents several advantages for the reduction of the design complexity, but brings new challenges for the test of the final circuit. The access to embedded cores, the integration of several test methods, and the optimization of the several cost factors are just a few of the several problems that need to be tackled during test planning. Within this context, this thesis proposes two test planning approaches that aim at reducing the test costs of a core-based system by means of hardware reuse and integration of the test planning into the design flow. The first approach considers systems whose cores are connected directly or through a functional bus. The test planning method consists of a comprehensive model that includes the definition of a multi-mode access mechanism inside the chip and a search algorithm for the exploration of the design space. The access mechanism model considers the reuse of functional connections as well as partial test buses, cores transparency, and other bypass modes. The test schedule is defined in conjunction with the access mechanism so that good trade-offs among the costs of pins, area, and test time can be sought. Furthermore, system power constraints are also considered. This expansion of concerns makes it possible an efficient, yet fine-grained search, in the huge design space of a reuse-based environment. Experimental results clearly show the variety of trade-offs that can be explored using the proposed model, and its effectiveness on optimizing the system test plan. Networks-on-chip are likely to become the main communication platform of systemson- chip. Thus, the second approach presented in this work proposes the reuse of the on-chip network for the test of the cores embedded into the systems that use this communication platform. A power-aware test scheduling algorithm aiming at exploiting the network characteristics to minimize the system test time is presented. The reuse strategy is evaluated considering a number of system configurations, such as different positions of the cores in the network, power consumption constraints and number of interfaces with the tester. Experimental results show that the parallelization capability of the network can be exploited to reduce the system test time, whereas area and pin overhead are strongly minimized. In this manuscript, the main problems of the test of core-based systems are firstly identified and the current solutions are discussed. The problems being tackled by this thesis are then listed and the test planning approaches are detailed. Both test planning techniques are validated for the recently released ITC’02 SoC Test Benchmarks, and further compared to other test planning methods of the literature. This comparison confirms the efficiency of the proposed methods.

A Modular and digitally programmable interface based on band-pass sigma-delta modulator for mixed-signal systems-on-chip

The focus of this thesis is to discuss the development and modeling of an interface architecture to be employed for interfacing analog signals in mixed-signal SOC. We claim that the approach that is going to be presented is able to achieve wide frequency range, and covers a large range of applications with constant performance, allied to digital configuration compatibility. Our primary assumptions are to use a fixed analog block and to promote application configurability in the digital domain, which leads to a mixed-signal interface. The use of a fixed analog block avoids the performance loss common to configurable analog blocks. The usage of configurability on the digital domain makes possible the use of all existing tools for high level design, simulation and synthesis to implement the target application, with very good performance prediction. The proposed approach utilizes the concept of frequency translation (mixing) of the input signal followed by its conversion to the ΣΔ domain, which makes possible the use of a fairly constant analog block, and also, a uniform treatment of input signal from DC to high frequencies. The programmability is performed in the ΣΔ digital domain where performance can be closely achieved according to application specification. The interface performance theoretical and simulation model are developed for design space exploration and for physical design support. Two prototypes are built and characterized to validate the proposed model and to implement some application examples. The usage of this interface as a multi-band parametric ADC and as a two channels analog multiplier and adder are shown. The multi-channel analog interface architecture is also presented. The characterization measurements support the main advantages of the approach proposed.

Redes-em-chip de baixo custo

Com as recentes tecnologias de fabricação é possível integrar milhões de transistores em um único chip, permitindo a criação dos chamados System-on-Chip (SoCs), que integram em um único chip um grande número de componentes (tipicamente blocos reutilizáveis conhecidos por núcleos). Quanto mais complexos forem estes sistemas, melhores técnicas de projeto serão necessárias para também reduzir o tempo e custo do projeto. Uma destas técnicas, chamada de Network-on-Chip (NoC), permite melhorar a performance da comunicação entre os núcleos e, ao mesmo tempo, fornecer uma plataforma de comunicação escalável e que pode ser reutilizada para um grande número de sistemas. Uma NoC pode ser definida como uma estrutura de roteadores e canais ponto-a-ponto que interconectam os núcleos de um sistema, provendo o suporte de comunicação entre eles. Os dados são transmitidos pela rede na forma de mensagens, que podem ser divididas em unidades menores chamadas de pacote. Uma das desvantagens desta plataforma de comunicação é o impacto na área do sistema causado pelos roteadores. Dentro deste contexto, este trabalho apresenta uma arquitetura de roteador de baixo custo, com o objetivo de permitir o uso de NoCs em sistemas onde a área do roteador representará um grande impacto no custo do sistema. A arquitetura deste roteador, chamado de Tonga, é baseada em um roteador chamado RASoC, um soft-core para SoCs. Nesta dissertação será apresentada também uma rede heterogênea, baseada na rede SoCIN, e composta por dois tipos de roteadores – RASoC e Tonga. Estes roteadores visam diferentes objetivos: Rasoc alcança uma maior performance comparada ao Tonga, mas ocupa área consideravelmente maior. Potencialmente, uma NoC heterogênea otimizada pode ser desenvolvida combinando estes roteadores, procurando o melhor compromisso entre área e latência. Os modelos desenvolvidos permitem a estimativa de área e do desempenho das arquiteturas de comunicação propostas e são apresentados resultados de performance para algumas aplicações.

The rite of passage from regular to connoisseur consumer: the role of the taste transformation ritual in the specialty coffee context

Apesar de o campo da cultura de consumo ter abordado o papel do ritual no consumo, definindo e descrevendo este constructo e explicando suas dimensões, significados culturais, elementos, componentes e práticas, assim como revelando a diferenciação nas práticas dos consumidores, nenhuma pesquisa ainda identificou como os consumidores, por meio de práticas de ritual, estabelecem e manipulam suas próprias diferenciações em relação a outros consumidores durante o rito de passagem deles de uma categoria cultural de pessoa para outra. Tendo como base conceitos-chaves da teoria sobre ritual, minha pesquisa aborda o papel do ritual no consume de apreciação. Conduzindo um estudo etnográfico sobre consumo de apreciação de cafés especiais, eu realizei uma imersão no campo, visitando e observando consumidores em cafeterias independentes de destaque na América do Norte – Toronto, Montreal, Seattle e Nova York – de agosto de 2013 a julho de 2014. Eu também realizei uma imersão no contexto de cafés especiais no Brasil em Belo Horizonte e São Paulo, de agosto de 2014 a janeiro de 2015, para comparar e contrastar as culturas de consume de cafés especiais de Brasil, Estados Unidos e Canadá. Eu usei entrevistas longas, observação participante, netnografia, introspecção e análise histórica de artigos de jornais para coletar os dados, que foram interpretados utilizando a abordagem hermenêutica, comparando os consumidores em diferentes estágios durante o rito de passagem de apreciação. Para estender meu entendimento sobre o consumo de apreciação, eu também coletei dados sobre o contexto de consumo de vinho. Nesta tese, eu introduzo a ideia de ritual de transformação do gosto, teorizando sobre o processo do rito de passagem de apreciação, que converte consumidores regulares em consumidores apreciadores. Minha pesquisa revela que consumidores apreciadores são amadores em diferentes estágios do rito de passagem de apreciação. Eles se transformam pelo estabelecimento e reforço de oposições entre o consume de massa e de apreciação. O ritual de transformação do gosto envolve os seguintes elementos: (1) variação nas escolhas de produtos de alta qualidade, (2) o lugar para realizar a degustação, (3) o momento da degustação, (4) o ato de degustar, (5) investimento de tempo e dinheiro, (6) aumento do capital subcultural e social, (7) perseverança no rito de passagem. Os consumidores apreciadores participam da comunidade de consumo de apreciação. Essa comunidade heterogênea é composta por profissionais excelentes, apreciadores e consumidores regulares. As forças que direcionam a comunidade, de acordo com o que foi identificado no estudo, são a produção de capital social e subcultural, emulação do profissional e das práticas de ritual de consumo, tensões de performance entre os membros da comunidade, amizade comercial e jogo de status. Eu desenvolvo uma ampla consideração teórica que desenvolve e estende um número de conceitos em relação a ritual e consumo, gosto, comunidade heterogênea e consumidores apreciadores.

Local Field Potentials in the Gustatory Cortex Carry Taste Information

It has been recently shownthat localfield potentials (LFPs)fromthe auditory and visual cortices carry information about sensory stimuli, but whether this is a universal property of sensory cortices remains to be determined. Moreover, little is known about the temporal dynamics of sensory information contained in LFPs following stimulus onset. Here we investigated the time course of the amount of stimulus information in LFPs and spikes from the gustatory cortex of awake rats subjected to tastants and water delivery on the tongue. We found that the phase and amplitude of multiple LFP frequencies carry information about stimuli, which have specific time courses after stimulus delivery. The information carried by LFP phase and amplitude was independent within frequency bands, since the joint information exhibited neither synergy nor redundancy. Tastant information in LFPs was also independent and had a different time course from the information carried by spikes. These findings support the hypothesis that the brain uses different frequency channels to dynamically code for multiple features of a stimulus.

Implementação e avaliação de máquinas de comitê em um ambiente com múltiplos processadores embarcados em um único chip

The number of applications based on embedded systems grows significantly every year, even with the fact that embedded systems have restrictions, and simple processing units, the performance of these has improved every day. However the complexity of applications also increase, a better performance will always be necessary. So even such advances, there are cases, which an embedded system with a single unit of processing is not sufficient to achieve the information processing in real time. To improve the performance of these systems, an implementation with parallel processing can be used in more complex applications that require high performance. The idea is to move beyond applications that already use embedded systems, exploring the use of a set of units processing working together to implement an intelligent algorithm. The number of existing works in the areas of parallel processing, systems intelligent and embedded systems is wide. However works that link these three areas to solve any problem are reduced. In this context, this work aimed to use tools available for FPGA architectures, to develop a platform with multiple processors to use in pattern classification with artificial neural networks

Wine classification by taste sensors made from ultra-thin films and using neural networks

This paper reports on a sensor array able to distinguish tastes and used to classify red wines. The array comprises sensing units made from Langmuir-Blodgett (LB) films of conducting polymers and lipids and layer-by-layer (LBL) films from chitosan deposited onto gold interdigitated electrodes. Using impedance spectroscopy as the principle of detection, we show that distinct clusters can be identified in principal component analysis (PCA) plots for six types of red wine. Distinction can be made with regard to vintage, vineyard and brands of the red wine. Furthermore, if the data are treated with artificial neural networks (ANNs), this artificial tongue can identify wine samples stored under different conditions. This is illustrated by considering 900 wine samples, obtained with 30 measurements for each of the five bottles of the six wines, which could be recognised with 100% accuracy using the algorithms Standard Backpropagation and Backpropagation momentum in the ANNs. (C) 2003 Elsevier B.V. All rights reserved.

A layer-by-layer film of chitosan in a taste sensor application

Chitosan is alternated with sulfonated polystyrene (PSS) to build layer-by-layer (LBL) films that are used as sensing units in an electronic tongue. Using impedance spectroscopy as the principle method of detection, an array using chitosan/PSS LBL film and a bare gold electrode as the sensing units was capable of distinguishing the basic tastes - salty, sweet, bitter, and sour - to a concentration below the human threshold. The suitability of chitosan as a sensing material was confirmed by using this sensor to distinguish red wines according to their vintage, vineyard, and brands.

Exploiting the versatility of taste sensors based on impedance spectroscopy

The versatility of sensor arrays made from nanostructured Langmuir-Blodgett (LB) and layer-by-layer (LBL) films is demonstrated in two ways. First, different combinations of sensing units are employed to distinguish the basic tastes, viz. sweet, sour, bitter, and salty tastes, produced, respectively, by small concentrations (down to 0.01 g/mol) of sucrose, HCl, quinine, and NaCl solutions. The sensing units are comprised of LB and/or LBL films from semiconducting polymers, a ruthenium complex, and sulfonated lignin. Then, sensor arrays were used to identify wines from different sources, with the high distinguishing ability being demonstrated in principal component analysis (PCA) plots. Particularly important was the fact that the sensing ability does not depend on specific interactions between analytes and the film materials, but a judicious choice of materials is, nevertheless, required for the materials to respond differently to a given sample. It is also shown that the interaction with the analyte may affect the morphology of the nanostructured films, as indicated with scanning electron microscopy. For instance, in wine analysis these changes are not irreversible and the original film morphology is retrieved if the sensing unit is washed with copious amounts of water, thus allowing the sensor unit to be reused.

Projeto de Sistemas Integrados de Propósito Geral Baseados em Redes em Chip Expandindo as Funcionalidades dos Roteadores para Execução de Operações: A plataforma IPNoSys

It bet on the next generation of computers as architecture with multiple processors and/or multicore processors. In this sense there are challenges related to features interconnection, operating frequency, the area on chip, power dissipation, performance and programmability. The mechanism of interconnection and communication it was considered ideal for this type of architecture are the networks-on-chip, due its scalability, reusability and intrinsic parallelism. The networks-on-chip communication is accomplished by transmitting packets that carry data and instructions that represent requests and responses between the processing elements interconnected by the network. The transmission of packets is accomplished as in a pipeline between the routers in the network, from source to destination of the communication, even allowing simultaneous communications between pairs of different sources and destinations. From this fact, it is proposed to transform the entire infrastructure communication of network-on-chip, using the routing mechanisms, arbitration and storage, in a parallel processing system for high performance. In this proposal, the packages are formed by instructions and data that represent the applications, which are executed on routers as well as they are transmitted, using the pipeline and parallel communication transmissions. In contrast, traditional processors are not used, but only single cores that control the access to memory. An implementation of this idea is called IPNoSys (Integrated Processing NoC System), which has an own programming model and a routing algorithm that guarantees the execution of all instructions in the packets, preventing situations of deadlock, livelock and starvation. This architecture provides mechanisms for input and output, interruption and operating system support. As proof of concept was developed a programming environment and a simulator for this architecture in SystemC, which allows configuration of various parameters and to obtain several results to evaluate it

The influence of sour taste and cold temperature in pharyngeal transit duration in patients with stroke

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)