Supramolecular functional assemblies with photo or chemical addressability

Supramolecular self-assembly represents a key technology for the spontaneous construction of nanoarchitectures and for the fabrication of materials with enhanced physical and chemical properties. In addition, a significant asset of supramolecular self-assemblies rests on their reversible formation, thanks to the kinetic lability of their non-covalent interactions. This dynamic nature can be exploited for the development of “self-healing” and “smart” materials towards the tuning of their functional properties upon various external factors. One particular intriguing objective in the field is to reach a high level of control over the shape and size of the supramolecular architectures, in order to produce well-defined functional nanostructures by rational design. In this direction, many investigations have been pursued toward the construction of self-assembled objects from numerous low-molecular weight scaffolds, for instance by exploiting multiple directional hydrogen-bonding interactions. In particular, nucleobases have been used as supramolecular synthons as a result of their efficiency to code for non-covalent interaction motifs. Among nucleobases, guanine represents the most versatile one, because of its different H-bond donor and acceptor sites which display self-complementary patterns of interactions. Interestingly, and depending on the environmental conditions, guanosine derivatives can form various types of structures. Most of the supramolecular architectures reported in this Thesis from guanosine derivatives require the presence of a cation which stabilizes, via dipole-ion interactions, the macrocyclic G-quartet that can, in turn, stack in columnar G-quadruplex arrangements. In addition, in absence of cations, guanosine can polymerize via hydrogen bonding to give a variety of supramolecular networks including linear ribbons. This complex supramolecular behavior confers to the guanine-guanine interactions their upper interest among all the homonucleobases studied. They have been subjected to intense investigations in various areas ranging from structural biology and medicinal chemistry – guanine-rich sequences are abundant in telomeric ends of chromosomes and promoter regions of DNA, and are capable of forming G-quartet based structures– to material science and nanotechnology. This Thesis, organized into five Chapters, describes mainly some recent advances in the form and function provided by self-assembly of guanine based systems. More generally, Chapter 4 will focus on the construction of supramolecular self-assemblies whose self-assembling process and self-assembled architectures can be controlled by light as external stimulus. Chapter 1 will describe some of the many recent studies of G-quartets in the general area of nanoscience. Natural G- quadruplexes can be useful motifs to build new structures and biomaterials such as self-assembled nanomachines, biosensors, therapeutic aptamer and catalysts. In Chapters 2-4 it is pointed out the core concept held in this PhD Thesis, i.e. the supramolecular organization of lipophilic guanosine derivatives with photo or chemical addressability. Chapter 2 will mainly focus on the use of cation-templated guanosine derivatives as a potential scaffold for designing functional materials with tailored physical properties, showing a new way to control the bottom-up realization of well-defined nanoarchitectures. In section 2.6.7, the self-assembly properties of compound 28a may be considered an example of open-shell moieties ordered by a supramolecular guanosine architecture showing a new (magnetic) property. Chapter 3 will report on ribbon-like structures, supramolecular architectures formed by guanosine derivatives that may be of interest for the fabrication of molecular nanowires within the framework of future molecular electronic applications. In section 3.4 we investigate the supramolecular polymerizations of derivatives dG 1 and G 30 by light scattering technique and TEM experiments. The obtained data reveal the presence of several levels of organization due to the hierarchical self-assembly of the guanosine units in ribbons that in turn aggregate in fibrillar or lamellar soft structures. The elucidation of these structures furnishes an explanation to the physical behaviour of guanosine units which display organogelator properties. Chapter 4 will describe photoresponsive self-assembling systems. Numerous research examples have demonstrated that the use of photochromic molecules in supramolecular self-assemblies is the most reasonable method to noninvasively manipulate their degree of aggregation and supramolecular architectures. In section 4.4 we report on the photocontrolled self-assembly of modified guanosine nucleobase E-42: by the introduction of a photoactive moiety at C8 it is possible to operate a photocontrol over the self-assembly of the molecule, where the existence of G-quartets can be alternately switched on and off. In section 4.5 we focus on the use of cyclodextrins as photoresponsive host-guest assemblies: αCD–azobenzene conjugates 47-48 (section 4.5.3) are synthesized in order to obtain a photoresponsive system exhibiting a fine photocontrollable degree of aggregation and self-assembled architecture. Finally, Chapter 5 contains the experimental protocols used for the research described in Chapters 2-4.

Studying MHC I-dependent CD8 + T cell responses in the model of murine cutaneous leishmaniasis

Der Ausheilung von Infektionen mit Leishmania major liegt die Sekretion von IFN- von sowohl CD4+ als auch CD8+ T Zellen zugrunde.rnAktuell konnte in der Literatur nur ein Epitop aus dem parasitären LACK Protein für eine effektive CD4+ T Zell-vermittelte Immunantwort beschrieben werden. Das Ziel der vorliegenden Arbeit bestand daher darin, mögliche MHC I abhängige CD8+ T Zell Antworten zu untersuchen. rnFür diesen Ansatz wurde als erstes der Effekt einer Vakzinierung mit LACK Protein fusioniert an die Protein-Transduktionsdomäne des HIV-1 (TAT) analysiert. Die Effektivität von TAT-LACK gegenüber CD8+ T Zellen wurde mittels in vivo Protein-Vakzinierung von resistenten C57BL/6 Mäusen in Depletions-Experimenten gezeigt.rnDie Prozessierung von Proteinen vor der Präsentation immunogener Peptide gegenüber T Zellen ist unbedingt erforderlich. Daher wurde in dieser Arbeit die Rolle des IFN--induzierbaren Immunoproteasoms bei der Prozessierung von parasitären Proteinen und Präsentation von Peptiden gebunden an MHC I Moleküle durch in vivo und in vitro Experimente untersucht. Es konnte in dieser Arbeit eine Immunoproteasom-unabhängige Prozessierung aufgezeigt werden.rnWeiterhin wurde Parasitenlysat (SLA) von sowohl Promastigoten als auch Amastigoten fraktioniert. In weiterführenden Experimenten können diese Fraktionen auf immunodominante Proteine/Peptide hin untersucht werden. rnLetztlich wurden Epitop-Vorhersagen für CD8+ T Zellen mittels computergestützer Software von beiden parasitären Lebensformen durchgeführt. 300 dieser Epitope wurden synthetisiert und werden in weiterführenden Experimenten zur Charakterisierung immunogener Eigenschaften weiter verwendet. rnIn ihrer Gesamtheit trägt die vorliegende Arbeit wesentlich zum Verständnis über die komplexen Mechanismen der Prozessierung und letztendlich zur Identifikation von möglichen CD8+ T Zell Epitopen bei. Ein detailiertes Verständnis der Prozessierung von CD8+ T Zell Epitopen von Leishmania major über den MHC Klasse I Weg ist von höchster Bedeutung. Die Charakterisierung sowie die Identifikation dieser Peptide wird einen maßgeblichen Einfluss auf die weiteren Entwicklungen von Vakzinen gegen diesen bedeutenden human-pathogenen Parasiten mit sich bringen. rn

Complex colloids by the emulsion solvent evaporation process

In this thesis, different complex colloids were prepared by the process of solvent evaporation from emulsion droplets (SEED). The term “complex” is used to include both an addressable functionality as well as the heterogeneous nature of the colloids.Firstly, as the SEED process was used throughout the thesis, its mechanism especially in regard to coalescence was investigated,. A wide variety of different techniques was employed to study the coalescence of nanodroplets during the evaporation of the solvent. Techniques such as DLS or FCS turned out not to be suitable methods to determine droplet coalescence because of their dependence on dilution. Thus, other methods were developed. TEM measurements were conducted on mixed polymeric emulsions with the results pointing to an absence of coalescence. However, these results were not quantifiable. FRET measurements on mixed polymeric emulsions also indicated an absence of coalescence. Again the results were not quantifiable. The amount of coalescence taking place was then quantified by the application of DC-FCCS. This method also allowed for measuring coalescence in other processes such as the miniemulsion polymerization or the polycondensation reaction on the interface of the droplets. By simulations it was shown that coalescence is not responsible for the usually observed broad size distribution of the produced particles. Therefore, the process itself, especially the emulsification step, needs to be improved to generate monodisperse colloids.rnThe Janus morphology is probably the best known among the different complex morphologies of nanoparticles. With the help of functional polymers, it was possible to marry click-chemistry to Janus particles. A large library of functional polymers was prepared by copolymerization and subsequent post-functionalization or by ATRP. The polymers were then used to generate Janus particles by the SEED process. Both dually functionalized Janus particles and particles with one functionalized face could be obtained. The latter were used for the quantification of functional groups on the surface of the Janus particles. For this, clickable fluorescent dyes were synthesized. The degree of functionality of the polymers was found to be closely mirrored in the degree of functionality of the surface. Thus, the marriage of click-chemistry to Janus particles was successful.Another complex morphology besides Janus particles are nanocapsules. Stimulus-responsive nanocapsules that show triggered release are a highly demanding and interesting system, as nanocapsules have promising applications in drug delivery and in self-healing materials. To achieve heterogeneity in the polymer shell, the stimulus-responsive block copolymer PVFc-b-PMMA was employed for the preparation of the capsules. The phase separation of the two blocks in the shell of the capsules led to a patchy morphology. These patches could then be oxidized resulting in morphology changes. In addition, swelling occurred because of the hydrophobic to hydrophilic transition of the patches induced by the oxidation. Due to the swelling, an encapsulated payload could diffuse out of the capsules, hence release was achieved.The concept of using block copolymers responsive to one stimulus for the preparation of stimulus-responsive capsules was extended to block copolymers responsive to more than one stimulus. Here, a block copolymer responsive to oxidation and a pH change as well as a block copolymer responsive to a pH change and temperature were studied in detail. The release from the nanocapsules could be regulated by tuning the different stimuli. In addition, by encapsulating stimuli-responsive payloads it was possible to selectively release a payload upon one stimulus but not upon the other one.In conclusion, the approaches taken in the course of this thesis demonstrate the broad applicability and usefulness of the SEED process to generate complex colloids. In addition, the experimental techniques established such as DC-FCCS will provide further insight into other research areas as well.

ADAM: Administration and Deployment of Adhoc Mesh Networks

Costly on-site node repairs in wireless mesh networks (WMNs) can be required due to misconfiguration, corrupt software updates, or unavailability during updates. We propose ADAM as a novel management framework that guarantees accessibility of individual nodes in these situations. ADAM uses a decentralised distribution mechanism and self-healing mechanisms for safe configuration and software updates. In order to implement the ADAM management and self-healing mechanisms, an easy-to-learn and extendable build system for a small footprint embedded Linux distribution for WMNs has been developed. The paper presents the ADAM concept, the build system for the Linux distribution and the management architecture.

Morphology and fracture of enamel

This study examines the inter-relation between enamel morphology and crack resistance by sectioning extracted human molars after loading to fracture. Cracks appear to initiate from tufts, hypocalcified defects at the enamel–dentin junction, and grow longitudinally around the enamel coat to produce failure. Microindentation corner cracks placed next to the tufts in the sections deflect along the tuft interfaces and occasionally penetrate into the adjacent enamel. Although they constitute weak interfaces, the tufts are nevertheless filled with organic matter, and appear to be stabilized against easy extension by self-healing, as well as by mutual stress-shielding and decussation, accounting at least in part for the capacity of tooth enamel to survive high functional forces.

Dynamic intraligamentary stabilization: novel technique for preserving the ruptured ACL

PURPOSE Replacement of the torn anterior cruciate ligament (ACL) with a transplant is today`s gold standard. A new technique for preserving and healing the torn ACL is presented. HYPOTHESIS a dynamic intraligamentary stabilization (DIS) that provides continuous postinjury stability of the knee and ACL in combination with biological improvement of the healing environment [leucocyte- and platelet-rich fibrin (L-PRF) and microfracturing] should enable biomechanically stable ACL self-healing. METHODS Ten sportive patients were treated by DIS employing an internal stabilizer to keep the unstable knee in a posterior translation, combined with microfracturing and platelet-rich fibrin induction at the rupture site to promote self-healing. Postoperative clinical [Tegner, Lysholm, International Knee Documentation Committee (IKDC), visual analogue scale patient satisfaction score] and radiological evaluation, as well as assessment of knee laxity was performed at 6 weeks, 3, 6, 12, and 24 months. RESULTS One patient had a re-rupture 5 months postoperative and was hence excluded from further follow-ups. The other nine patients presented the following outcomes at 24 months: median Lysholm score of 100; IKDC score of 98 (97-100); median Tegner score of 6 (range 9-5); anterior translation difference of 1.4 mm (-1 to 3 mm); median satisfaction score of 9.8 (9-10). MRI showed scarring and continuity of the ligament in all patients. CONCLUSIONS DIS combined with microfracturing and L-PRF resulted in stable clinical and radiological healing of the torn ACL in all but one patient of this first series. They attained normal knee scores, reported excellent satisfaction and could return to their previous levels of sporting activity. LEVEL OF EVIDENCE Case series with no comparison group, Level IV.

Transforming growth factor beta signaling is essential for the autonomous formation of cartilage-like tissue by expanded chondrocytes.

Cartilage is a tissue with limited self-healing potential. Hence, cartilage defects require surgical attention to prevent or postpone the development of osteoarthritis. For cell-based cartilage repair strategies, in particular autologous chondrocyte implantation, articular chondrocytes are isolated from cartilage and expanded in vitro to increase the number of cells required for therapy. During expansion, the cells lose the competence to autonomously form a cartilage-like tissue, that is in the absence of exogenously added chondrogenic growth factors, such as TGF-βs. We hypothesized that signaling elicited by autocrine and/or paracrine TGF-β is essential for the formation of cartilage-like tissue and that alterations within the TGF-β signaling pathway during expansion interfere with this process. Primary bovine articular chondrocytes were harvested and expanded in monolayer culture up to passage six and the formation of cartilage tissue was investigated in high density pellet cultures grown for three weeks. Chondrocytes expanded for up to three passages maintained the potential for autonomous cartilage-like tissue formation. After three passages, however, exogenous TGF-β1 was required to induce the formation of cartilage-like tissue. When TGF-β signaling was blocked by inhibiting the TGF-β receptor 1 kinase, the autonomous formation of cartilage-like tissue was abrogated. At the initiation of pellet culture, chondrocytes from passage three and later showed levels of transcripts coding for TGF-β receptors 1 and 2 and TGF-β2 to be three-, five- and five-fold decreased, respectively, as compared to primary chondrocytes. In conclusion, the autonomous formation of cartilage-like tissue by expanded chondrocytes is dependent on signaling induced by autocrine and/or paracrine TGF-β. We propose that a decrease in the expression of the chondrogenic growth factor TGF-β2 and of the TGF-β receptors in expanded chondrocytes accounts for a decrease in the activity of the TGF-β signaling pathway and hence for the loss of the potential for autonomous cartilage-like tissue formation.

Dynamic Intraligamentary Stabilization (DIS) for treatment of acute anterior cruciate ligament ruptures: case series experience of the first three years.

BACKGROUND In recent years, the scientific discussion has focused on new strategies to enable a torn anterior cruciate ligament (ACL) to heal into mechanically stable scar tissue. Dynamic intraligamentary stabilization (DIS) was first performed in a pilot study of 10 patients. The purpose of the current study was to evaluate whether DIS would lead to similarly sufficient stability and good clinical function in a larger case series. METHODS Acute ACL ruptures were treated by using an internal stabilizer, combined with anatomical repositioning of torn bundles and microfracturing to promote self-healing. Clinical assessment (Tegner, Lysholm, IKDC, and visual analogue scale [VAS] for patient satisfaction scores) and assessment of knee laxity was performed at 3, 6, 12, and 24 months. A one-sample design with a non-inferiority margin was chosen to compare the preoperative and postoperative IKDS and Lysholm scores. RESULTS 278 patients with a 6:4 male to female ratio were included. Average patient age was 31 years. Preoperative mean IKDC, Lysholm, and Tegner scores were 98.8, 99.3, and 5.1 points, respectively. The mean anteroposterior (AP) translation difference from the healthy contralateral knee was 4.7 mm preoperatively. After DIS treatment, the mean 12-month IKDC, Lysholm, and Tegner scores were 93.6, 96.2, and 4.9 points, respectively, and the mean AP translation difference was 2.3 mm. All these outcomes were significantly non-inferior to the preoperative or healthy contralateral values (p < 0.0001). Mean patient satisfaction was 8.8 (VAS 0-10). Eight ACL reruptures occurred and 3 patients reported insufficient subjective stability of the knee at the end of the study period. CONCLUSIONS Anatomical repositioning, along with DIS and microfracturing, leads to clinically stable healing of the torn ACL in the large majority of patients. Most patients exhibited almost normal knee function, reported excellent satisfaction, and were able to return to their previous levels of sporting activity. Moreover, this strategy resulted in stable healing of all sutured menisci, which could lower the rate of osteoarthritic changes in future. The present findings support the discussion of a new paradigm in ACL treatment based on preservation and self-healing of the torn ligament.

Run-Time Scalable Hardware for Reconfigurable Systems

La optimización de parámetros tales como el consumo de potencia, la cantidad de recursos lógicos empleados o la ocupación de memoria ha sido siempre una de las preocupaciones principales a la hora de diseñar sistemas embebidos. Esto es debido a que se trata de sistemas dotados de una cantidad de recursos limitados, y que han sido tradicionalmente empleados para un propósito específico, que permanece invariable a lo largo de toda la vida útil del sistema. Sin embargo, el uso de sistemas embebidos se ha extendido a áreas de aplicación fuera de su ámbito tradicional, caracterizadas por una mayor demanda computacional. Así, por ejemplo, algunos de estos sistemas deben llevar a cabo un intenso procesado de señales multimedia o la transmisión de datos mediante sistemas de comunicaciones de alta capacidad. Por otra parte, las condiciones de operación del sistema pueden variar en tiempo real. Esto sucede, por ejemplo, si su funcionamiento depende de datos medidos por el propio sistema o recibidos a través de la red, de las demandas del usuario en cada momento, o de condiciones internas del propio dispositivo, tales como la duración de la batería. Como consecuencia de la existencia de requisitos de operación dinámicos es necesario ir hacia una gestión dinámica de los recursos del sistema. Si bien el software es inherentemente flexible, no ofrece una potencia computacional tan alta como el hardware. Por lo tanto, el hardware reconfigurable aparece como una solución adecuada para tratar con mayor flexibilidad los requisitos variables dinámicamente en sistemas con alta demanda computacional. La flexibilidad y adaptabilidad del hardware requieren de dispositivos reconfigurables que permitan la modificación de su funcionalidad bajo demanda. En esta tesis se han seleccionado las FPGAs (Field Programmable Gate Arrays) como los dispositivos más apropiados, hoy en día, para implementar sistemas basados en hardware reconfigurable De entre todas las posibilidades existentes para explotar la capacidad de reconfiguración de las FPGAs comerciales, se ha seleccionado la reconfiguración dinámica y parcial. Esta técnica consiste en substituir una parte de la lógica del dispositivo, mientras el resto continúa en funcionamiento. La capacidad de reconfiguración dinámica y parcial de las FPGAs es empleada en esta tesis para tratar con los requisitos de flexibilidad y de capacidad computacional que demandan los dispositivos embebidos. La propuesta principal de esta tesis doctoral es el uso de arquitecturas de procesamiento escalables espacialmente, que son capaces de adaptar su funcionalidad y rendimiento en tiempo real, estableciendo un compromiso entre dichos parámetros y la cantidad de lógica que ocupan en el dispositivo. A esto nos referimos con arquitecturas con huellas escalables. En particular, se propone el uso de arquitecturas altamente paralelas, modulares, regulares y con una alta localidad en sus comunicaciones, para este propósito. El tamaño de dichas arquitecturas puede ser modificado mediante la adición o eliminación de algunos de los módulos que las componen, tanto en una dimensión como en dos. Esta estrategia permite implementar soluciones escalables, sin tener que contar con una versión de las mismas para cada uno de los tamaños posibles de la arquitectura. De esta manera se reduce significativamente el tiempo necesario para modificar su tamaño, así como la cantidad de memoria necesaria para almacenar todos los archivos de configuración. En lugar de proponer arquitecturas para aplicaciones específicas, se ha optado por patrones de procesamiento genéricos, que pueden ser ajustados para solucionar distintos problemas en el estado del arte. A este respecto, se proponen patrones basados en esquemas sistólicos, así como de tipo wavefront. Con el objeto de poder ofrecer una solución integral, se han tratado otros aspectos relacionados con el diseño y el funcionamiento de las arquitecturas, tales como el control del proceso de reconfiguración de la FPGA, la integración de las arquitecturas en el resto del sistema, así como las técnicas necesarias para su implementación. Por lo que respecta a la implementación, se han tratado distintos aspectos de bajo nivel dependientes del dispositivo. Algunas de las propuestas realizadas a este respecto en la presente tesis doctoral son un router que es capaz de garantizar el correcto rutado de los módulos reconfigurables dentro del área destinada para ellos, así como una estrategia para la comunicación entre módulos que no introduce ningún retardo ni necesita emplear recursos configurables del dispositivo. El flujo de diseño propuesto se ha automatizado mediante una herramienta denominada DREAMS. La herramienta se encarga de la modificación de las netlists correspondientes a cada uno de los módulos reconfigurables del sistema, y que han sido generadas previamente mediante herramientas comerciales. Por lo tanto, el flujo propuesto se entiende como una etapa de post-procesamiento, que adapta esas netlists a los requisitos de la reconfiguración dinámica y parcial. Dicha modificación la lleva a cabo la herramienta de una forma completamente automática, por lo que la productividad del proceso de diseño aumenta de forma evidente. Para facilitar dicho proceso, se ha dotado a la herramienta de una interfaz gráfica. El flujo de diseño propuesto, y la herramienta que lo soporta, tienen características específicas para abordar el diseño de las arquitecturas dinámicamente escalables propuestas en esta tesis. Entre ellas está el soporte para el realojamiento de módulos reconfigurables en posiciones del dispositivo distintas a donde el módulo es originalmente implementado, así como la generación de estructuras de comunicación compatibles con la simetría de la arquitectura. El router has sido empleado también en esta tesis para obtener un rutado simétrico entre nets equivalentes. Dicha posibilidad ha sido explotada para aumentar la protección de circuitos con altos requisitos de seguridad, frente a ataques de canal lateral, mediante la implantación de lógica complementaria con rutado idéntico. Para controlar el proceso de reconfiguración de la FPGA, se propone en esta tesis un motor de reconfiguración especialmente adaptado a los requisitos de las arquitecturas dinámicamente escalables. Además de controlar el puerto de reconfiguración, el motor de reconfiguración ha sido dotado de la capacidad de realojar módulos reconfigurables en posiciones arbitrarias del dispositivo, en tiempo real. De esta forma, basta con generar un único bitstream por cada módulo reconfigurable del sistema, independientemente de la posición donde va a ser finalmente reconfigurado. La estrategia seguida para implementar el proceso de realojamiento de módulos es diferente de las propuestas existentes en el estado del arte, pues consiste en la composición de los archivos de configuración en tiempo real. De esta forma se consigue aumentar la velocidad del proceso, mientras que se reduce la longitud de los archivos de configuración parciales a almacenar en el sistema. El motor de reconfiguración soporta módulos reconfigurables con una altura menor que la altura de una región de reloj del dispositivo. Internamente, el motor se encarga de la combinación de los frames que describen el nuevo módulo, con la configuración existente en el dispositivo previamente. El escalado de las arquitecturas de procesamiento propuestas en esta tesis también se puede beneficiar de este mecanismo. Se ha incorporado también un acceso directo a una memoria externa donde se pueden almacenar bitstreams parciales. Para acelerar el proceso de reconfiguración se ha hecho funcionar el ICAP por encima de la máxima frecuencia de reloj aconsejada por el fabricante. Así, en el caso de Virtex-5, aunque la máxima frecuencia del reloj deberían ser 100 MHz, se ha conseguido hacer funcionar el puerto de reconfiguración a frecuencias de operación de hasta 250 MHz, incluyendo el proceso de realojamiento en tiempo real. Se ha previsto la posibilidad de portar el motor de reconfiguración a futuras familias de FPGAs. Por otro lado, el motor de reconfiguración se puede emplear para inyectar fallos en el propio dispositivo hardware, y así ser capaces de evaluar la tolerancia ante los mismos que ofrecen las arquitecturas reconfigurables. Los fallos son emulados mediante la generación de archivos de configuración a los que intencionadamente se les ha introducido un error, de forma que se modifica su funcionalidad. Con el objetivo de comprobar la validez y los beneficios de las arquitecturas propuestas en esta tesis, se han seguido dos líneas principales de aplicación. En primer lugar, se propone su uso como parte de una plataforma adaptativa basada en hardware evolutivo, con capacidad de escalabilidad, adaptabilidad y recuperación ante fallos. En segundo lugar, se ha desarrollado un deblocking filter escalable, adaptado a la codificación de vídeo escalable, como ejemplo de aplicación de las arquitecturas de tipo wavefront propuestas. El hardware evolutivo consiste en el uso de algoritmos evolutivos para diseñar hardware de forma autónoma, explotando la flexibilidad que ofrecen los dispositivos reconfigurables. En este caso, los elementos de procesamiento que componen la arquitectura son seleccionados de una biblioteca de elementos presintetizados, de acuerdo con las decisiones tomadas por el algoritmo evolutivo, en lugar de definir la configuración de las mismas en tiempo de diseño. De esta manera, la configuración del core puede cambiar cuando lo hacen las condiciones del entorno, en tiempo real, por lo que se consigue un control autónomo del proceso de reconfiguración dinámico. Así, el sistema es capaz de optimizar, de forma autónoma, su propia configuración. El hardware evolutivo tiene una capacidad inherente de auto-reparación. Se ha probado que las arquitecturas evolutivas propuestas en esta tesis son tolerantes ante fallos, tanto transitorios, como permanentes y acumulativos. La plataforma evolutiva se ha empleado para implementar filtros de eliminación de ruido. La escalabilidad también ha sido aprovechada en esta aplicación. Las arquitecturas evolutivas escalables permiten la adaptación autónoma de los cores de procesamiento ante fluctuaciones en la cantidad de recursos disponibles en el sistema. Por lo tanto, constituyen un ejemplo de escalabilidad dinámica para conseguir un determinado nivel de calidad, que puede variar en tiempo real. Se han propuesto dos variantes de sistemas escalables evolutivos. El primero consiste en un único core de procesamiento evolutivo, mientras que el segundo está formado por un número variable de arrays de procesamiento. La codificación de vídeo escalable, a diferencia de los codecs no escalables, permite la decodificación de secuencias de vídeo con diferentes niveles de calidad, de resolución temporal o de resolución espacial, descartando la información no deseada. Existen distintos algoritmos que soportan esta característica. En particular, se va a emplear el estándar Scalable Video Coding (SVC), que ha sido propuesto como una extensión de H.264/AVC, ya que este último es ampliamente utilizado tanto en la industria, como a nivel de investigación. Para poder explotar toda la flexibilidad que ofrece el estándar, hay que permitir la adaptación de las características del decodificador en tiempo real. El uso de las arquitecturas dinámicamente escalables es propuesto en esta tesis con este objetivo. El deblocking filter es un algoritmo que tiene como objetivo la mejora de la percepción visual de la imagen reconstruida, mediante el suavizado de los "artefactos" de bloque generados en el lazo del codificador. Se trata de una de las tareas más intensivas en procesamiento de datos de H.264/AVC y de SVC, y además, su carga computacional es altamente dependiente del nivel de escalabilidad seleccionado en el decodificador. Por lo tanto, el deblocking filter ha sido seleccionado como prueba de concepto de la aplicación de las arquitecturas dinámicamente escalables para la compresión de video. La arquitectura propuesta permite añadir o eliminar unidades de computación, siguiendo un esquema de tipo wavefront. La arquitectura ha sido propuesta conjuntamente con un esquema de procesamiento en paralelo del deblocking filter a nivel de macrobloque, de tal forma que cuando se varía del tamaño de la arquitectura, el orden de filtrado de los macrobloques varia de la misma manera. El patrón propuesto se basa en la división del procesamiento de cada macrobloque en dos etapas independientes, que se corresponden con el filtrado horizontal y vertical de los bloques dentro del macrobloque. Las principales contribuciones originales de esta tesis son las siguientes: - El uso de arquitecturas altamente regulares, modulares, paralelas y con una intensa localidad en sus comunicaciones, para implementar cores de procesamiento dinámicamente reconfigurables. - El uso de arquitecturas bidimensionales, en forma de malla, para construir arquitecturas dinámicamente escalables, con una huella escalable. De esta forma, las arquitecturas permiten establecer un compromiso entre el área que ocupan en el dispositivo, y las prestaciones que ofrecen en cada momento. Se proponen plantillas de procesamiento genéricas, de tipo sistólico o wavefront, que pueden ser adaptadas a distintos problemas de procesamiento. - Un flujo de diseño y una herramienta que lo soporta, para el diseño de sistemas reconfigurables dinámicamente, centradas en el diseño de las arquitecturas altamente paralelas, modulares y regulares propuestas en esta tesis. - Un esquema de comunicaciones entre módulos reconfigurables que no introduce ningún retardo ni requiere el uso de recursos lógicos propios. - Un router flexible, capaz de resolver los conflictos de rutado asociados con el diseño de sistemas reconfigurables dinámicamente. - Un algoritmo de optimización para sistemas formados por múltiples cores escalables que optimice, mediante un algoritmo genético, los parámetros de dicho sistema. Se basa en un modelo conocido como el problema de la mochila. - Un motor de reconfiguración adaptado a los requisitos de las arquitecturas altamente regulares y modulares. Combina una alta velocidad de reconfiguración, con la capacidad de realojar módulos en tiempo real, incluyendo el soporte para la reconfiguración de regiones que ocupan menos que una región de reloj, así como la réplica de un módulo reconfigurable en múltiples posiciones del dispositivo. - Un mecanismo de inyección de fallos que, empleando el motor de reconfiguración del sistema, permite evaluar los efectos de fallos permanentes y transitorios en arquitecturas reconfigurables. - La demostración de las posibilidades de las arquitecturas propuestas en esta tesis para la implementación de sistemas de hardware evolutivos, con una alta capacidad de procesamiento de datos. - La implementación de sistemas de hardware evolutivo escalables, que son capaces de tratar con la fluctuación de la cantidad de recursos disponibles en el sistema, de una forma autónoma. - Una estrategia de procesamiento en paralelo para el deblocking filter compatible con los estándares H.264/AVC y SVC que reduce el número de ciclos de macrobloque necesarios para procesar un frame de video. - Una arquitectura dinámicamente escalable que permite la implementación de un nuevo deblocking filter, totalmente compatible con los estándares H.264/AVC y SVC, que explota el paralelismo a nivel de macrobloque. El presente documento se organiza en siete capítulos. En el primero se ofrece una introducción al marco tecnológico de esta tesis, especialmente centrado en la reconfiguración dinámica y parcial de FPGAs. También se motiva la necesidad de las arquitecturas dinámicamente escalables propuestas en esta tesis. En el capítulo 2 se describen las arquitecturas dinámicamente escalables. Dicha descripción incluye la mayor parte de las aportaciones a nivel arquitectural realizadas en esta tesis. Por su parte, el flujo de diseño adaptado a dichas arquitecturas se propone en el capítulo 3. El motor de reconfiguración se propone en el 4, mientras que el uso de dichas arquitecturas para implementar sistemas de hardware evolutivo se aborda en el 5. El deblocking filter escalable se describe en el 6, mientras que las conclusiones finales de esta tesis, así como la descripción del trabajo futuro, son abordadas en el capítulo 7. ABSTRACT The optimization of system parameters, such as power dissipation, the amount of hardware resources and the memory footprint, has been always a main concern when dealing with the design of resource-constrained embedded systems. This situation is even more demanding nowadays. Embedded systems cannot anymore be considered only as specific-purpose computers, designed for a particular functionality that remains unchanged during their lifetime. Differently, embedded systems are now required to deal with more demanding and complex functions, such as multimedia data processing and high-throughput connectivity. In addition, system operation may depend on external data, the user requirements or internal variables of the system, such as the battery life-time. All these conditions may vary at run-time, leading to adaptive scenarios. As a consequence of both the growing computational complexity and the existence of dynamic requirements, dynamic resource management techniques for embedded systems are needed. Software is inherently flexible, but it cannot meet the computing power offered by hardware solutions. Therefore, reconfigurable hardware emerges as a suitable technology to deal with the run-time variable requirements of complex embedded systems. Adaptive hardware requires the use of reconfigurable devices, where its functionality can be modified on demand. In this thesis, Field Programmable Gate Arrays (FPGAs) have been selected as the most appropriate commercial technology existing nowadays to implement adaptive hardware systems. There are different ways of exploiting reconfigurability in reconfigurable devices. Among them is dynamic and partial reconfiguration. This is a technique which consists in substituting part of the FPGA logic on demand, while the rest of the device continues working. The strategy followed in this thesis is to exploit the dynamic and partial reconfiguration of commercial FPGAs to deal with the flexibility and complexity demands of state-of-the-art embedded systems. The proposal of this thesis to deal with run-time variable system conditions is the use of spatially scalable processing hardware IP cores, which are able to adapt their functionality or performance at run-time, trading them off with the amount of logic resources they occupy in the device. This is referred to as a scalable footprint in the context of this thesis. The distinguishing characteristic of the proposed cores is that they rely on highly parallel, modular and regular architectures, arranged in one or two dimensions. These architectures can be scaled by means of the addition or removal of the composing blocks. This strategy avoids implementing a full version of the core for each possible size, with the corresponding benefits in terms of scaling and adaptation time, as well as bitstream storage memory requirements. Instead of providing specific-purpose architectures, generic architectural templates, which can be tuned to solve different problems, are proposed in this thesis. Architectures following both systolic and wavefront templates have been selected. Together with the proposed scalable architectural templates, other issues needed to ensure the proper design and operation of the scalable cores, such as the device reconfiguration control, the run-time management of the architecture and the implementation techniques have been also addressed in this thesis. With regard to the implementation of dynamically reconfigurable architectures, device dependent low-level details are addressed. Some of the aspects covered in this thesis are the area constrained routing for reconfigurable modules, or an inter-module communication strategy which does not introduce either extra delay or logic overhead. The system implementation, from the hardware description to the device configuration bitstream, has been fully automated by modifying the netlists corresponding to each of the system modules, which are previously generated using the vendor tools. This modification is therefore envisaged as a post-processing step. Based on these implementation proposals, a design tool called DREAMS (Dynamically Reconfigurable Embedded and Modular Systems) has been created, including a graphic user interface. The tool has specific features to cope with modular and regular architectures, including the support for module relocation and the inter-module communications scheme based on the symmetry of the architecture. The core of the tool is a custom router, which has been also exploited in this thesis to obtain symmetric routed nets, with the aim of enhancing the protection of critical reconfigurable circuits against side channel attacks. This is achieved by duplicating the logic with an exactly equal routing. In order to control the reconfiguration process of the FPGA, a Reconfiguration Engine suited to the specific requirements set by the proposed architectures was also proposed. Therefore, in addition to controlling the reconfiguration port, the Reconfiguration Engine has been enhanced with the online relocation ability, which allows employing a unique configuration bitstream for all the positions where the module may be placed in the device. Differently to the existing relocating solutions, which are based on bitstream parsers, the proposed approach is based on the online composition of bitstreams. This strategy allows increasing the speed of the process, while the length of partial bitstreams is also reduced. The height of the reconfigurable modules can be lower than the height of a clock region. The Reconfiguration Engine manages the merging process of the new and the existing configuration frames within each clock region. The process of scaling up and down the hardware cores also benefits from this technique. A direct link to an external memory where partial bitstreams can be stored has been also implemented. In order to accelerate the reconfiguration process, the ICAP has been overclocked over the speed reported by the manufacturer. In the case of Virtex-5, even though the maximum frequency of the ICAP is reported to be 100 MHz, valid operations at 250 MHz have been achieved, including the online relocation process. Portability of the reconfiguration solution to today's and probably, future FPGAs, has been also considered. The reconfiguration engine can be also used to inject faults in real hardware devices, and this way being able to evaluate the fault tolerance offered by the reconfigurable architectures. Faults are emulated by introducing partial bitstreams intentionally modified to provide erroneous functionality. To prove the validity and the benefits offered by the proposed architectures, two demonstration application lines have been envisaged. First, scalable architectures have been employed to develop an evolvable hardware platform with adaptability, fault tolerance and scalability properties. Second, they have been used to implement a scalable deblocking filter suited to scalable video coding. Evolvable Hardware is the use of evolutionary algorithms to design hardware in an autonomous way, exploiting the flexibility offered by reconfigurable devices. In this case, processing elements composing the architecture are selected from a presynthesized library of processing elements, according to the decisions taken by the algorithm, instead of being decided at design time. This way, the configuration of the array may change as run-time environmental conditions do, achieving autonomous control of the dynamic reconfiguration process. Thus, the self-optimization property is added to the native self-configurability of the dynamically scalable architectures. In addition, evolvable hardware adaptability inherently offers self-healing features. The proposal has proved to be self-tolerant, since it is able to self-recover from both transient and cumulative permanent faults. The proposed evolvable architecture has been used to implement noise removal image filters. Scalability has been also exploited in this application. Scalable evolvable hardware architectures allow the autonomous adaptation of the processing cores to a fluctuating amount of resources available in the system. Thus, it constitutes an example of the dynamic quality scalability tackled in this thesis. Two variants have been proposed. The first one consists in a single dynamically scalable evolvable core, and the second one contains a variable number of processing cores. Scalable video is a flexible approach for video compression, which offers scalability at different levels. Differently to non-scalable codecs, a scalable video bitstream can be decoded with different levels of quality, spatial or temporal resolutions, by discarding the undesired information. The interest in this technology has been fostered by the development of the Scalable Video Coding (SVC) standard, as an extension of H.264/AVC. In order to exploit all the flexibility offered by the standard, it is necessary to adapt the characteristics of the decoder to the requirements of each client during run-time. The use of dynamically scalable architectures is proposed in this thesis with this aim. The deblocking filter algorithm is the responsible of improving the visual perception of a reconstructed image, by smoothing blocking artifacts generated in the encoding loop. This is one of the most computationally intensive tasks of the standard, and furthermore, it is highly dependent on the selected scalability level in the decoder. Therefore, the deblocking filter has been selected as a proof of concept of the implementation of dynamically scalable architectures for video compression. The proposed architecture allows the run-time addition or removal of computational units working in parallel to change its level of parallelism, following a wavefront computational pattern. Scalable architecture is offered together with a scalable parallelization strategy at the macroblock level, such that when the size of the architecture changes, the macroblock filtering order is modified accordingly. The proposed pattern is based on the division of the macroblock processing into two independent stages, corresponding to the horizontal and vertical filtering of the blocks within the macroblock. The main contributions of this thesis are: - The use of highly parallel, modular, regular and local architectures to implement dynamically reconfigurable processing IP cores, for data intensive applications with flexibility requirements. - The use of two-dimensional mesh-type arrays as architectural templates to build dynamically reconfigurable IP cores, with a scalable footprint. The proposal consists in generic architectural templates, which can be tuned to solve different computational problems. •A design flow and a tool targeting the design of DPR systems, focused on highly parallel, modular and local architectures. - An inter-module communication strategy, which does not introduce delay or area overhead, named Virtual Borders. - A custom and flexible router to solve the routing conflicts as well as the inter-module communication problems, appearing during the design of DPR systems. - An algorithm addressing the optimization of systems composed of multiple scalable cores, which size can be decided individually, to optimize the system parameters. It is based on a model known as the multi-dimensional multi-choice Knapsack problem. - A reconfiguration engine tailored to the requirements of highly regular and modular architectures. It combines a high reconfiguration throughput with run-time module relocation capabilities, including the support for sub-clock reconfigurable regions and the replication in multiple positions. - A fault injection mechanism which takes advantage of the system reconfiguration engine, as well as the modularity of the proposed reconfigurable architectures, to evaluate the effects of transient and permanent faults in these architectures. - The demonstration of the possibilities of the architectures proposed in this thesis to implement evolvable hardware systems, while keeping a high processing throughput. - The implementation of scalable evolvable hardware systems, which are able to adapt to the fluctuation of the amount of resources available in the system, in an autonomous way. - A parallelization strategy for the H.264/AVC and SVC deblocking filter, which reduces the number of macroblock cycles needed to process the whole frame. - A dynamically scalable architecture that permits the implementation of a novel deblocking filter module, fully compliant with the H.264/AVC and SVC standards, which exploits the macroblock level parallelism of the algorithm. This document is organized in seven chapters. In the first one, an introduction to the technology framework of this thesis, specially focused on dynamic and partial reconfiguration, is provided. The need for the dynamically scalable processing architectures proposed in this work is also motivated in this chapter. In chapter 2, dynamically scalable architectures are described. Description includes most of the architectural contributions of this work. The design flow tailored to the scalable architectures, together with the DREAMs tool provided to implement them, are described in chapter 3. The reconfiguration engine is described in chapter 4. The use of the proposed scalable archtieectures to implement evolvable hardware systems is described in chapter 5, while the scalable deblocking filter is described in chapter 6. Final conclusions of this thesis, and the description of future work, are addressed in chapter 7.

A novel FPGA-based evolvable hardware system based on multiple processing arrays

In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.

Técnicas avanzadas de diseño y análisis de rendimiento en despliegues inalámbricos en interiores

En los últimos tiempos, el tráfico generado por los usuarios de redes móviles ha crecido de manera muy notable, y se prevé que dicho crecimiento se mantenga de manera continuada a lo largo de los próximos años. El tráfico gestionado por redes móviles se ha multiplicado por cinco entre los años 2010 y 2013, y las predicciones señalan un aumento de diez veces entre 2013 y 2019. De este tráfico que deben gestionar las redes móviles, una gran parte se genera en el interior de edificios. En la actualidad, éste oscila entre el 70% y el 80% del tráfico móvil total, y este porcentaje se prevé que aumente hasta cerca del 95% en los próximos años. En esta situación, con el tráfico móvil aumentando de manera exponencial, especialmente en interiores, el despliegue de soluciones específicas para estos entornos se antoja imprescindible para evitar situaciones de saturación constante de las redes móviles. Desde el punto de vista de los operadores móviles, estas soluciones permitirán limitar los problemas de cobertura, mejorar la eficiencia del uso de recursos radio y reducir el coste de las infraestructuras. Asimismo, desde el punto de vista de los usuarios, estos despliegues específicos en interiores permitirán suministrar de manera continua altas tasas de transferencia y satisfacer los altos requisitos de calidad de servicio que demandan los servicios en tiempo real. La complejidad de las actuaciones a realizar para llevar a cabo el despliegue de soluciones específicas en interiores varía considerablemente según el tipo de entorno al que están destinadas. Por un lado, las soluciones en escenarios de tipo residencial se caracterizan por despliegues masivos de transmisores realizados por los propios usuarios. De esta manera, no hay posibilidad de realizar ningún tipo de planificación previa que permita la optimización del rendimiento y solo se puede recurrir, para la mejora de éste, a métodos de autoconfiguración y autooptimización. Por otro lado, las soluciones en entornos empresariales se caracterizan por la necesidad de realizar una labor de diseño y planificación previa, cuya dificultad estará asociada a las dimensiones del escenario de despliegue y al número de transmisores necesarias. De esta labor de diseño y de la configuración de los elementos involucrados en la solución desplegada dependerá el funcionamiento adecuado de la red, el rendimiento conseguido y la calidad del servicio que se podrá suministrar a través de ésta. En esta Tesis Doctoral se abordan dos de los problemas principales en el ámbito del despliegue de soluciones específicas de interiores. El primero de ellos es la dificultad para estimar la capacidad y el rendimiento que puede garantizarse mediante soluciones autodesplegadas, y el segundo es la complejidad de diseñar y configurar despliegues de soluciones específicas de interiores en entornos empresariales que requieran un número de transmisores considerable. En el ámbito de los autodespliegues en escenarios residenciales, las principales contribuciones originales de esta Tesis Doctoral se centran en el diseño, desarrollo e implementación de procedimientos que permitan de manera sencilla y precisa la estimación de la capacidad y el rendimiento en autodespliegues. Por otro lado, en el ámbito de los despliegues en escenarios empresariales, las aportaciones originales de esta Tesis consisten en el desarrollo de nuevas técnicas que permitan el diseño automático de soluciones específicas de interiores en estos entornos. Los resultados obtenidos han permitido la creación de herramientas específicas para el análisis del rendimiento de autodespliegues en escenarios residenciales reales y para el diseño y configuración de despliegues en escenarios empresariales. Estas herramientas permiten sistematizar la aplicación práctica de las contribuciones de la presente Tesis Doctoral. ABSTRACT In recent times, the traffic generated by users of mobile networks has grown very significantly, and this increase is expected to continue steadily over the next few years. Traffic carried by mobile networks has increased fivefold between 2010 and 2013, and forecasts indicate a tenfold increase between 2013 and 2019. Furthermore, a great part of this traffic is generated inside buildings. Currently, between 70% and 80% of mobile traffic occurs inside buildings, and this percentage is expected to increase to about 95% in the coming years. In this situation, with mobile traffic growing exponentially, especially indoors, the deployment of specific solutions for these environments can be essential to avoid a constant saturation of mobile networks. On the one hand, from the point of view of mobile operators, these solutions will help to reduce the problems of coverage, improve the efficiency of radio resource usage and reduce the cost of infrastructures. Also, from the point of view of users, these specific indoor deployments can both guarantee high data transfer rates and meet the high quality of service requirements associated with real-time services. The complexity of the actions required to carry out the deployment of specific solutions indoors varies considerably depending on the type of scenario they are conceived to. On the one hand, residential scenarios are characterized by massive deployments of base stations made by the user, so there is no possibility of any prior planning. In this case only self-configuration, selfoptimization and self-healing methods can be considered for performance optimization. On the other hand, specific in-building solutions in enterprise environments requires a previous design and planning phase, whose difficulty is closely associated with the size of the deployment scenario and the number of base stations required. The design and configuration of the elements included in the solution will determine its performance and the quality of service that can be guaranteed. The objective of the present Thesis is to address two of the main issues related to specific indoor solutions, such as the difficulty of assessing the capacity and the performance which can be guaranteed by means of self-deployments and the complexity of the design and configuration of deployments in enterprise environments requiring a large number of base stations. The main contribution of this thesis consists of the development of techniques and simple tools for design and performance analysis of indoor wireless networks deployments. The main results include the development of procedures for assessing the capacity and performance of self-deployments in residential scenarios, the performance analysis of real residential self-deployments using the proposed procedures and the development of techniques for the automatic design of wireless networks in enterprise environments. The results obtained have allowed the creation of specific software tools for both the performance analysis of self-deployments and the design and deployment of in-building solutions in enterprise scenarios. These software tools are conceived to systematize the practical application of the contributions of this Thesis.

From The Holding Cell to the Holding Environment: Applying an Intersubjective Approach into Trauma Treatment with Women in the Correctional Setting

Abstract This paper investigates themes and parallels related to the traumatic experiences women face within the correctional setting and how these experiences influence women's behavior choices that increase their risk of recidivism. Intersubjective Systems Theory is used to conceptualize the distinct dynamics and impact of trauma with this particular population. Intersubjectivity also informs the changes needed to create an environment that would help women in correctional settings to heal, avoid recidivism, and foster successful community reintegration. Principles from Intersubjective Systems Theory are reviewed in this paper to demonstrate: (a) how developmental trauma impacts the lives of incarcerated women, (b) how these women's attempts at self-healing are often maladaptive and lead to arrests, (c) how the current climate in corrections leads to retraumatization and promotes later recidivism, and (d) what changes in the corrections system would promote optimal healing and better outcomes for incarcerated women. Improved outcomes are defined as healthy boundaries, empowerment in choice of relationships, improvement of social support and occupational skills, and reduction of relapse and recidivism.

Environmental health, indigenous identity, cultural representations and the production of ecological consciousness in Northern Ontario

The primary goal of this research is to document local perspectives by presenting a set of commentaries and meanings, in the form of narratives, related to environmental health conceptions on an Oji-Cree reserve in Northeastern Ontario, Canada. Through an ethnographic case study, this research explores how the modern-day production of a sociocentric and ecocentric self, as ethnic marker and moral category, is contributing to environmental/community health and well-being on Native reserves. Cultural representations of personhood and community based on the Medicine Wheel model, as a cognitive model, create an ontological paradigm that promotes a holistic foundation for human behaviour and interaction, as well as healthy, sustainable communities.

3D-based reconstruction using growing neural gas landmark: application to rapid prototyping in shoe last manufacturing

Customizing shoe manufacturing is one of the great challenges in the footwear industry. It is a production model change where design adopts not only the main role, but also the main bottleneck. It is therefore necessary to accelerate this process by improving the accuracy of current methods. Rapid prototyping techniques are based on the reuse of manufactured footwear lasts so that they can be modified with CAD systems leading rapidly to new shoe models. In this work, we present a shoe last fast reconstruction method that fits current design and manufacturing processes. The method is based on the scanning of shoe last obtaining sections and establishing a fixed number of landmarks onto those sections to reconstruct the shoe last 3D surface. Automated landmark extraction is accomplished through the use of the self-organizing network, the growing neural gas (GNG), which is able to topographically map the low dimensionality of the network to the high dimensionality of the contour manifold without requiring a priori knowledge of the input space structure. Moreover, our GNG landmark method is tolerant to noise and eliminates outliers. Our method accelerates up to 12 times the surface reconstruction and filtering processes used by the current shoe last design software. The proposed method offers higher accuracy compared with methods with similar efficiency as voxel grid.

3D reconstruction of medical images from slices automatically landmarked with growing neural models

In this study, we utilise a novel approach to segment out the ventricular system in a series of high resolution T1-weighted MR images. We present a brain ventricles fast reconstruction method. The method is based on the processing of brain sections and establishing a fixed number of landmarks onto those sections to reconstruct the ventricles 3D surface. Automated landmark extraction is accomplished through the use of the self-organising network, the growing neural gas (GNG), which is able to topographically map the low dimensionality of the network to the high dimensionality of the contour manifold without requiring a priori knowledge of the input space structure. Moreover, our GNG landmark method is tolerant to noise and eliminates outliers. Our method accelerates the classical surface reconstruction and filtering processes. The proposed method offers higher accuracy compared to methods with similar efficiency as Voxel Grid.