Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.

Distributed Region-Based Memory Allocation and Synchronization

We present DRASync, a region-based allocator that implements a global address space abstraction for MPI programs with pointer-based data structures. The main features of DRASync are: (a) it amortizes communication among nodes to allow efficient parallel allocation in a global address space; (b) it takes advantage of bulk deallocation and good locality with pointer-based data structures; (c) it supports ownership semantics of regions by nodes akin to reader–writer locks, which makes for a high-level, intuitive synchronization tool in MPI programs, without sacrificing message-passing performance. We evaluate DRASync against a state-of-the-art distributed allocator and find that it produces comparable performance while offering a higher-level abstraction to programmers.

WCET analysis considering contention on memory bus in COTS-based multicores

The usage of COTS-based multicores is becoming widespread in the field of embedded systems. Providing realtime guarantees at design-time is a pre-requisite to deploy real-time systems on these multicores. This necessitates the consideration of the impact of the contention due to shared low-level hardware resources on the Worst-Case Execution Time (WCET) of the tasks. As a step towards this aim, this paper first identifies the different factors that make the WCET analysis a challenging problem in a typical COTS-based multicore system. Then, we propose and prove, a mathematically correct method to determine tight upper bounds on the WCET of the tasks, when they are co-scheduled on different cores.

Response time analysis of COTS-Based multicores considering the contention on the shared memory bus

The current industry trend is towards using Commercially available Off-The-Shelf (COTS) based multicores for developing real time embedded systems, as opposed to the usage of custom-made hardware. In typical implementation of such COTS-based multicores, multiple cores access the main memory via a shared bus. This often leads to contention on this shared channel, which results in an increase of the response time of the tasks. Analyzing this increased response time, considering the contention on the shared bus, is challenging on COTS-based systems mainly because bus arbitration protocols are often undocumented and the exact instants at which the shared bus is accessed by tasks are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. This paper makes three contributions towards analyzing tasks scheduled on COTS-based multicores. Firstly, we describe a method to model the memory access patterns of a task. Secondly, we apply this model to analyze the worst case response time for a set of tasks. Although the required parameters to obtain the request profile can be obtained by static analysis, we provide an alternative method to experimentally obtain them by using performance monitoring counters (PMCs). We also compare our work against an existing approach and show that our approach outperforms it by providing tighter upper-bound on the number of bus requests generated by a task.

Finding an upper bound on the increase in execution time due to contention on the memory bus in COTS-based multicore systems

Contention on the memory bus in COTS based multicore systems is becoming a major determining factor of the execution time of a task. Analyzing this extra execution time is non-trivial because (i) bus arbitration protocols in such systems are often undocumented and (ii) the times when the memory bus is requested to be used are not explicitly controlled by the operating system scheduler; they are instead a result of cache misses. We present a method for finding an upper bound on the extra execution time of a task due to contention on the memory bus in COTS based multicore systems. This method makes no assumptions on the bus arbitration protocol (other than assuming that it is work-conserving).

Vibrational behaviour of bcc Cu-based shape memory alloys close to the martensitic transition

Experimental data from ultrasonic and inelastic neutron scattering measurements are analyzed for different families of Cu-based shape-memory alloys. It is shown that the transition occurs at a value, independent of composition and alloy family, of the ratio between the elastic constants associated with the two shears necessary to accomplish the lattice distortion from the bcc to the close-packed structure. The zone boundary frequency of the TA2[110] branch evaluated at the transition point (TM), weakly depends, for each family, on composition. A linear relationship between this frequency and the inverse of the elastic constant C', both quantities evaluated at TM, has been found, in agreement with the prediction of a Landau model proposed for martensitic transformations.

Time-based prospective memory in children with autism spectrum disorder

In this study, for the first time, prospective memory was investigated in 11 school-aged children with autism spectrum disorders and 11 matched neurotypical controls. A computerised time-based prospective memory task was embedded in a visuospatial working memory test and required participants to remember to respond to certain target times. Controls had significantly more correct prospective memory responses than the autism spectrum group. Moreover, controls checked the time more often and increased time-monitoring more steeply as the target times approached. These differences in time-checking may suggest that prospective memory in autism spectrum disorders is affected by reduced self-initiated processing as indicated by reduced task monitoring.

The development of time-based prospective memory in childhood: the role of working memory updating

This large-scale study examined the development of time-based prospective memory (PM) across childhood and the roles that working memory updating and time monitoring play in driving age effects in PM performance. One hundred and ninety-seven children aged 5 to 14 years completed a time-based PM task where working memory updating load was manipulated within individuals using a dual task design. Results revealed age-related increases in PM performance across childhood. Working memory updating load had a negative impact on PM performance and monitoring behavior in older children, but this effect was smaller in younger children. Moreover, the frequency as well as the pattern of time monitoring predicted children’s PM performance. Our interpretation of these results is that processes involved in children’s PM may show a qualitative shift over development from simple, nonstrategic monitoring behavior to more strategic monitoring based on internal temporal models that rely specifically on working memory updating resources. We discuss this interpretation with regard to possible trade-off effects in younger children as well as alternative accounts.