Power Capping: What Works, What Does Not

Peak power consumption is the first order design constraint of data centers. Though peak power consumption is rarely, if ever, observed, the entire data center facility must prepare for it, leading to inefficient usage of its resources. The most prominent way for addressing this issue is to limit the power consumption of the data center IT facility far below its theoretical peak value. Many approaches have been proposed to achieve that, based on the same small set of enforcement mechanisms, but there has been no corresponding work on systematically examining the advantages and disadvantages of each such mechanism. In the absence of such a study,it is unclear what is the optimal mechanism for a given computing environment, which can lead to unnecessarily poor performance if an inappropriate scheme is used. This paper fills this gap by comparing for the first time five widely used power capping mechanisms under the same hardware/software setting. We also explore possible alternative power capping mechanisms beyond what has been previously proposed and evaluate them under the same setup. We systematically analyze the strengths and weaknesses of each mechanism, in terms of energy efficiency, overhead, and predictable behavior. We show how these mechanisms can be combined in order to implement an optimal power capping mechanism which reduces the slow down compared to the most widely used mechanism by up to 88%. Our results provide interesting insights regarding the different trade-offs of power capping techniques, which will be useful for designing and implementing highly efficient power capping in the future. 

Pre-Processing Power Traces to Defeat Random Clocking Countermeasures

We describe a pre-processing correlation attack on an FPGA implementation of AES, protected with a random clocking countermeasure that exhibits complex variations in both the location and amplitude of the power consumption patterns of the AES rounds. It is demonstrated that the merged round patterns can be pre-processed to identify and extract the individual round amplitudes, enabling a successful power analysis attack. We show that the requirement of the random clocking countermeasure to provide a varying execution time between processing rounds can be exploited to select a sub-set of data where sufficient current decay has occurred, further improving the attack. In comparison with the countermeasure's estimated security of 3 million traces from an integration attack, we show that through application of our proposed techniques that the countermeasure can now be broken with as few as 13k traces.

Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment

Static timing analysis provides the basis for setting the clock period of a microprocessor core, based on its worst-case critical path. However, depending on the design, this critical path is not always excited and therefore dynamic timing margins exist that can theoretically be exploited for the benefit of better speed or lower power consumption (through voltage scaling). This paper introduces predictive instruction-based dynamic clock adjustment as a technique to trim dynamic timing margins in pipelined microprocessors. To this end, we exploit the different timing requirements for individual instructions during the dynamically varying program execution flow without the need for complex circuit-level measures to detect and correct timing violations. We provide a design flow to extract the dynamic timing information for the design using post-layout dynamic timing analysis and we integrate the results into a custom cycle-accurate simulator. This simulator allows annotation of individual instructions with their impact on timing (in each pipeline stage) and rapidly derives the overall code execution time for complex benchmarks. The design methodology is illustrated at the microarchitecture level, demonstrating the performance and power gains possible on a 6-stage OpenRISC in-order general purpose processor core in a 28nm CMOS technology. We show that employing instruction-dependent dynamic clock adjustment leads on average to an increase in operating speed by 38% or to a reduction in power consumption by 24%, compared to traditional synchronous clocking, which at all times has to respect the worst-case timing identified through static timing analysis.

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

The area and power consumption of low-density parity check (LDPC) decoders are typically dominated by embedded memories. To alleviate such high memory costs, this paper exploits the fact that all internal memories of a LDPC decoder are frequently updated with new data. These unique memory access statistics are taken advantage of by replacing all static standard-cell based memories (SCMs) of a prior-art LDPC decoder implementation by dynamic SCMs (D-SCMs), which are designed to retain data just long enough to guarantee reliable operation. The use of D-SCMs leads to a 44% reduction in silicon area of the LDPC decoder compared to the use of static SCMs. The low-power LDPC decoder architecture with refresh-free D-SCMs was implemented in a 90nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600 Mbps (as required by the IEEE 802.11n standard).

Pre-Processing Power Traces with a Phase-Sensitive Detector

As cryptographic implementations are increasingly subsumed as functional blocks within larger systems on chip, it becomes more difficult to identify the power consumption signatures of cryptographic operations amongst other unrelated processing activities. In addition, at higher clock frequencies, the current decay between successive processing rounds is only partial, making it more difficult to apply existing pattern matching techniques in side-channel analysis. We show however, through the use of a phase-sensitive detector, that power traces can be pre-processed to generate a filtered output which exhibits an enhanced round pattern, enabling the identification of locations on a device where encryption operations are occurring and also assisting with the re-alignment of power traces for side-channel attacks.

Runtime Support for Adaptive Power Capping on Heterogeneous SoCs

Power capping is a fundamental method for reducing the energy consumption of a wide range of modern computing environments, ranging from mobile embedded systems to datacentres. Unfortunately, maximising performance and system efficiency under static power caps remains challenging, while maximising performance under dynamic power caps has been largely unexplored. We present an adaptive power capping method that reduces the power consumption and maximizes the performance of heterogeneous SoCs for mobile and server platforms. Our technique combines power capping with coordinated DVFS, data partitioning and core allocations on a heterogeneous SoC with ARM processors and FPGA resources. We design our framework as a run-time system based on OpenMP and OpenCL to utilise the heterogeneous resources. We evaluate it through five data-parallel benchmarks on the Xilinx SoC which allows fully voltage and frequency control. Our experiments show a significant performance boost of 30% under dynamic power caps with concurrent execution on ARM and FPGA, compared to a naive separate approach.

Organic addittives in zinc electrowinning and electrodeposition of Fe-Mo-P alloys as cathodes for chlorate production

Ce projet de travail est divisé en deux études principales: (a) l’influence des certains additifs organiques sur la consommation d’énergie et la pureté du métal de zinc déposé dans le processus d’extraction électrolytique, et (b) l’électrodéposition des alliages binaires et ternaires de Fe-Mo et Fe-Mo-P sur des substrats d’acier doux afin d’agir comme cathodes pour la production de chlorate. (a) Parmi les sept différents additifs organiques examinés, les sels des liquides ioniques ont réussi à augmenter le rendement du courant jusqu’à 95,1% comparé à 88,7% qui a obtenu à partir de l’électrolyte standard en présence des ions de Sb3+. La réduction maximale de la consommation d’énergie de ~173 kWh tonne-1 a été obtenue en ajoutant de 3 mg dm-3 du chlorure de 1-butyl-3-méthylimidazolium dans le même électrolyte. La teneur en plomb dans le dépôt de zinc est réduite de 26,5 ppm à 5,1-5,6 ppm en utilisant les sels des liquides ioniques. (b) Des différents binaires Fe-Mo et ternaires Fe-Mo-P alliages ont été électrodéposés sur des substrats d’acier doux. Les alliages préparés ont une tenure en Mo entre 21-47 at.% et une tenure en P de 0 à 16 at.%. L’activité électrocatalytique de ces alliages vers la réaction de dégagement d’hydrogène (RDH) a été étudiée dans des solutions de chlorure de sodium. La réduction maximale de la surtension de RDH de ~313 mV a été obtenue par l’alliage ternaire préparé Fe54Mo30P16 par rapport à celle obtenue pour l’acier doux. La rugosité de surface et l’activité intrinsèque des revêtements de Fe-Mo-P peuvent être l’origine du comportement prometteur de ces électrocatalyseurs vers la RDH.

A low-complexity self-calibrating adaptive quadrature receiver

In this paper digital part of a self-calibrating quadrature-receiver is described, containing a digital calibration-engine. The blind source-separation-based calibration-engine eliminates the RF-impairments in real-time hence improving the receiver's performance without the need for test/pilot tones, trimming or use of power-hungry discrete components. Furthermore, an efficient time-multiplexed calibration-engine architecture is proposed and implemented on an FPGA utilising a reduced-range multiplier structure. The use of reduced-range multipliers results in substantial reduction of area as well as power consumption without a compromise in performance when compared with an efficiently designed general purpose multiplier. The performance of the calibration-engine does not depend on the modulation format or the constellation size of the received signal; hence it can be easily integrated into the digital signal processing paths of any receiver.

Design of a power-aware digital image rejection receiver

This paper deals with and details the design of a power-aware adaptive digital image rejection receiver based on blind-source-separation that alleviates the RF analog front-end impairments. Power-aware system design at the RTL level without having to redesign arithmetic circuits is used to reduce the power consumption in nomadic devices. Power-aware multipliers with configurable precision are used to trade-off the image-rejection-ratio (IRR) performance with power consumption. Results of the simulation case studies demonstrate that the IRR performance of the power-aware system is comparable to that of the normal implementation albeit degraded slightly, but well within the acceptable limits.

Reference clock design for low power and low phase noise with temperature compensation

Thesis (Ph.D.)--University of Washington, 2016-03

Projecto e concepção de instalação frigorífica a NH3, para uma unidade de congelação de frangos em contínuo, na Venezuela

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Mecânica

Estudo técnico-económico para otimização do projeto e implementação de uma bomba de calor "heat machine"

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Mecânica

Optimizing the embedded heaters position in the pultrusion process using finite element analysis

This study is based on a previous experimental work in which embedded cylindrical heaters were applied to a pultrusion machine die, and resultant energetic performance compared with that achieved with the former heating system based on planar resistances. The previous work allowed to conclude that the use of embedded resistances enhances significantly the energetic performance of pultrusion process, leading to 57% decrease of energy consumption. However, the aforementioned study was developed with basis on an existing pultrusion die, which only allowed a single relative position for the heaters. In the present work, new relative positions for the heaters were investigated in order to optimize heat distribution process and energy consumption. Finite Elements Analysis was applied as an efficient tool to identify the best relative position of the heaters into the die, taking into account the usual parameters involved in the process and the control system already tested in the previous study. The analysis was firstly developed with basis on eight cylindrical heaters located in four different location plans. In a second phase, in order to refine the results, a new approach was adopted using sixteen heaters with the same total power. Final results allow to conclude that the correct positioning of the heaters can contribute to about 10% of energy consumption reduction, decreasing the production costs and leading to a better eco-efficiency of pultrusion process.

Estudo comparativo entre o sistema convencional de arrefecimento e o arrefecedor evaporativo para os edifícios industriais portugueses

Em Portugal existem muitos espaços comerciais e industriais em que as necessidades térmicas de arrefecimento são muito superiores às necessidades de aquecimento devido aos ganhos internos que advêm da existência de equipamentos e da iluminação dos edifícios, assim como, da presença das pessoas. A instalação de sistemas convencionais de ar condicionado para espaços comerciais e industriais de grande dimensão está geralmente associada ao transporte de grandes caudais de ar, e consequentemente, a elevados consumos de energia primária, e também, elevados custos de investimento, de manutenção e de operação. O arrefecedor evaporativo é uma solução de climatização com elevada eficiência energética, cujo princípio de funcionamento promove a redução do consumo de energia primária nos edifícios. A metodologia utilizada baseou-se na criação de uma ferramenta informática de simulação do funcionamento de um protótipo de um arrefecedor evaporativo. Foi efetuada a modelação matemática das variáveis dinâmicas envolvidas, dos processos de transferência de calor e de massa, assim como dos balanços de energia que ocorrem no arrefecedor evaporativo. A ferramenta informática desenvolvida permite o dimensionamento do protótipo do arrefecedor evaporativo, sendo determinadas as caraterísticas técnicas (potência térmica, caudal, eficiência energética, consumo energético e consumo e água) de acordo com o tipo de edifício e com as condições climatéricas do ar exterior. Foram selecionados três dimensionamentos de arrefecedores evaporativos, representativos de condições reais de uma gama baixa, média e elevada de caudais de ar. Os resultados obtidos nas simulações mostram que a potência de arrefecimento (5,6 kW, 16,0 kW e 32,8 kW) e o consumo de água (8 l/h, 23,9 l/h e 48,96 l/h) aumentam com o caudal de ar do arrefecedor, 5.000 m3/h, 15.000 m3/h e 30.000 m3/h, respetivamente. A eficácia de permuta destes arrefecedores evaporativos, foi de 69%, 66% e 67%, respetivamente. Verificou-se que a alteração de zona climática de V1 para V2 implicou um aumento de 39% na potência de arrefecimento e de 20% no consumo de água, e que, a alteração de zona climática de V2 para V3 implicou um aumento de 39% na potência de arrefecimento e de 39% no consumo de água. O arrefecedor evaporativo apresenta valores de consumo de energia elétrica entre 40% a 80% inferiores aos dos sistemas de arrefecimento convencionais, sendo este efeito mais intenso quando a zona climática de verão se torna mais severa.

Real-Time Tariffs for Electric Vehicles in Wind Power based Power Systems

The use of Electric Vehicles (EVs) will change significantly the planning and management of power systems in a near future. This paper proposes a real-time tariff strategy for the charge process of the EVs. The main objective is to evaluate the influence of real-time tariffs in the EVs owners’ behaviour and also the impact in load diagram. The paper proposes the energy price variation according to the relation between wind generation and power consumption. The proposed strategy was tested in two different days in the Danish power system. January 31st and August 13th 2013 were selected because of the high quantities of wind generation. The main goal is to evaluate the changes in the EVs charging diagram with the energy price preventing wind curtailment.