Approche efficace pour la conception des architectures multiprocesseurs sur puce électronique

Les systèmes multiprocesseurs sur puce électronique (On-Chip Multiprocessor [OCM]) sont considérés comme les meilleures structures pour occuper l'espace disponible sur les circuits intégrés actuels. Dans nos travaux, nous nous intéressons à un modèle architectural, appelé architecture isométrique de systèmes multiprocesseurs sur puce, qui permet d'évaluer, de prédire et d'optimiser les systèmes OCM en misant sur une organisation efficace des nœuds (processeurs et mémoires), et à des méthodologies qui permettent d'utiliser efficacement ces architectures. Dans la première partie de la thèse, nous nous intéressons à la topologie du modèle et nous proposons une architecture qui permet d'utiliser efficacement et massivement les mémoires sur la puce. Les processeurs et les mémoires sont organisés selon une approche isométrique qui consiste à rapprocher les données des processus plutôt que d'optimiser les transferts entre les processeurs et les mémoires disposés de manière conventionnelle. L'architecture est un modèle maillé en trois dimensions. La disposition des unités sur ce modèle est inspirée de la structure cristalline du chlorure de sodium (NaCl), où chaque processeur peut accéder à six mémoires à la fois et où chaque mémoire peut communiquer avec autant de processeurs à la fois. Dans la deuxième partie de notre travail, nous nous intéressons à une méthodologie de décomposition où le nombre de nœuds du modèle est idéal et peut être déterminé à partir d'une spécification matricielle de l'application qui est traitée par le modèle proposé. Sachant que la performance d'un modèle dépend de la quantité de flot de données échangées entre ses unités, en l'occurrence leur nombre, et notre but étant de garantir une bonne performance de calcul en fonction de l'application traitée, nous proposons de trouver le nombre idéal de processeurs et de mémoires du système à construire. Aussi, considérons-nous la décomposition de la spécification du modèle à construire ou de l'application à traiter en fonction de l'équilibre de charge des unités. Nous proposons ainsi une approche de décomposition sur trois points : la transformation de la spécification ou de l'application en une matrice d'incidence dont les éléments sont les flots de données entre les processus et les données, une nouvelle méthodologie basée sur le problème de la formation des cellules (Cell Formation Problem [CFP]), et un équilibre de charge de processus dans les processeurs et de données dans les mémoires. Dans la troisième partie, toujours dans le souci de concevoir un système efficace et performant, nous nous intéressons à l'affectation des processeurs et des mémoires par une méthodologie en deux étapes. Dans un premier temps, nous affectons des unités aux nœuds du système, considéré ici comme un graphe non orienté, et dans un deuxième temps, nous affectons des valeurs aux arcs de ce graphe. Pour l'affectation, nous proposons une modélisation des applications décomposées en utilisant une approche matricielle et l'utilisation du problème d'affectation quadratique (Quadratic Assignment Problem [QAP]). Pour l'affectation de valeurs aux arcs, nous proposons une approche de perturbation graduelle, afin de chercher la meilleure combinaison du coût de l'affectation, ceci en respectant certains paramètres comme la température, la dissipation de chaleur, la consommation d'énergie et la surface occupée par la puce. Le but ultime de ce travail est de proposer aux architectes de systèmes multiprocesseurs sur puce une méthodologie non traditionnelle et un outil systématique et efficace d'aide à la conception dès la phase de la spécification fonctionnelle du système.

Affectation de composantes basée sur des contraintes énergétiques dans une architecture multiprocesseurs en trois dimensions

La lithographie et la loi de Moore ont permis des avancées extraordinaires dans la fabrication des circuits intégrés. De nos jours, plusieurs systèmes très complexes peuvent être embarqués sur la même puce électronique. Les contraintes de développement de ces systèmes sont tellement grandes qu’une bonne planification dès le début de leur cycle de développement est incontournable. Ainsi, la planification de la gestion énergétique au début du cycle de développement est devenue une phase importante dans la conception de ces systèmes. Pendant plusieurs années, l’idée était de réduire la consommation énergétique en ajoutant un mécanisme physique une fois le circuit créé, comme par exemple un dissipateur de chaleur. La stratégie actuelle est d’intégrer les contraintes énergétiques dès les premières phases de la conception des circuits. Il est donc essentiel de bien connaître la dissipation d’énergie avant l’intégration des composantes dans une architecture d’un système multiprocesseurs de façon à ce que chaque composante puisse fonctionner efficacement dans les limites de ses contraintes thermiques. Lorsqu’une composante fonctionne, elle consomme de l’énergie électrique qui est transformée en dégagement de chaleur. Le but de ce mémoire est de trouver une affectation efficace des composantes dans une architecture de multiprocesseurs en trois dimensions en tenant compte des limites des facteurs thermiques de ce système.

Analysis of scoliosis trunk deformities using ICA

This paper describes a method for analyzing scoliosis trunk deformities using Independent Component Analysis (ICA). Our hypothesis is that ICA can capture the scoliosis deformities visible on the trunk. Unlike Principal Component Analysis (PCA), ICA gives local shape variation and assumes that the data distribution is not normal. 3D torso images of 56 subjects including 28 patients with adolescent idiopathic scoliosis and 28 healthy subjects are analyzed using ICA. First, we remark that the independent components capture the local scoliosis deformities as the shoulder variation, the scapula asymmetry and the waist deformation. Second, we note that the different scoliosis curve types are characterized by different combinations of specific independent components.

Dielectric Properties of Ba5Nb4O15 Ceramic

Ceramic dielectrics with high dielectric constant in the microwave frequency range are used as filters, oscillators [I], etc. in microwave integrated circuits (MICs) particularly in modern communication systems like cellular telephones and satellite communications. Such ceramics, known as 'dielectric resonators (DRs),donot only offer miniaturisation and reduce the weight of the microwave components. but also improve the efficiency of MICs

Synthesis, Characterization and Properties of Ca5A2TiO12 (A=Nb, Ta) Ceramic Dielectric Materials for Applications in Microwave Telecommunication Systems

Microwave ceramic dielectric materials Ca5Nb2TiO12 and Ca5Ta2TiO12 have been prepared by a conventional solid-state ceramic process. The structure was studied by X-ray diffraction and the dielectric properties were characterized at microwave frequencies. The ceramics posses a relatively high dielectric constant, very low dielectric loss (Q5 x f > 30000GHz) and small temperature variation of resonant frequency. These materials are potential candidates for dielectric resonator applications in microwave integrated circuits. [DOI: 10. 1 143/JJAP.41.3834]

Development and Analysis of a Compact Dual-Band Coplanar Antenna

The coplanar wave guide is an attractive device in microwave integrated circuits due to its uniplanar nature, ease of fabrication and low production cost. Several attempts are already done to explore the radiating modes in coplanar wave guide transmission lines. Usually coplanar wave guides are excited by an SMA connector with its centre conductor connected to the exact middle of the centre strip and the outer ground conductor to the two ground strips. The mode excited on it is purely a bound mode. The E-field distribution in the two slots are out of phase and there for cancels at the far field. This thesis addresses an attempt to excite an in phase E-field distribution in the two slots of the co planar wave guide by employing a feed asymmetry, in order to get radiation from the two large slot discontinuities of the coplanar waveguide. The omni directional distribution of the radiating energy can be achieved by widening the centre strip.The first part of the thesis deals with the investigations on the resonance phenomena of conventional coplanar waveguides at higher frequency bands. Then an offset fed open circuited coplanar waveguide supporting resonance/radiation phenomena is analyzed. Finally, a novel compact co planar antenna geometry with dual band characteristics, suitable for mobile terminal applications is designed and characterized using the inferences from the above study.

Cap mòbil amb tecnologia led RGBW controlat per DMX

Disseny tant a nivell de hardware com de software d’un cap mòbil amb tecnologia led RGBW controlat pel protocol DMX512. Aquest projecte es limita al disseny i a la realització de tots els elements de software i hardware necessaris per crear un prototipus de cap mòbil que pugui ser controlat mitjançant el protocol DMX. Per tant, està encarat completament cap a la vessant electrònica i de programació sense fer referència als materials i elements constructius utilitzats o sobre el disseny i estètica del producte

La travesía obsoleta: la indefensión del consumidor

La obsolescencia programada es el deseo de tener algo un poco más nuevo, un poco mejor, un poco más rápido de lo necesario. El texto estudia este fenómeno a la luz del Estatuto del Consumidor – Ley 1480 de 2011 para determinar si el consumidor colombiano está suficientemente protegido con él.

Big and little Meccano

The emergence of the mechanical bond during the past 25 years is giving chemistry a fillip in more ways than one. While its arrival on the scene is already impacting materials science and molecular nanotechnology, it is providing a new lease of life to chemical synthesis where mechanical bond formation Occurs as a consequence of the all-important templation Orchestrated by molecular recognition and self-assembly. The way in which covalent bond formation activates noncovalent bonding interactions, switching on molecular recognition that leads to self-assembly, and the template-directed synthesis of mechanically interlocked molecules-of which the so-called catenanes and rotaxanes may be regarded as the prototypes-has introduced a level of integration into chemical synthesis that has not previously been attained jointly at the supramolecular and molecular levels. The challenge now is to carry this I vel of integration during molecular synthesis beyond relatively small molecules into the realms of precisely functionalized extended molecular Structures and superstructures that perform functions in a collective manner as the key sources of instruction, activation, and performance in multi-component integrated Circuits and devices. These forays into organic chemistry by a scientific nomad are traced through thick and thin from the Athens of the North to the Windy City by Lake Michigan with interludes on the edge of the Canadian Shield beside Lake Ontario, in the Socialist Republic of South Yorkshire, on the Plains of Cheshire beside the Wirral, in the Midlands in the Heartland of Albion, and in the City of Angels beside the Peaceful Sea. (C) 2008 Elsevier Ltd. All rights reserved.

Optimization of electroless copper plating on polyethylene films modified by surface grafting of vinyl ether of monoethanolamine

Metallized plastics have recently received significant interest for their useful applications in electronic devices such as for integrated circuits, packaging, printed circuits and sensor applications. In this work the metallized films were developed by electroless copper plating of polyethylene films grafted with vinyl ether of monoethanoleamine. There are several techniques for metal deposition on surface of polymers such as evaporation, sputtering, electroless plating and electrolysis. In this work the metallized films were developed by electroless copper plating of polyethylene films grafted with vinyl ether of monoethanoleamine. Polyethylene films were subjected to gamma-radiation induced surface graft copolymerization with vinyl ether of monoethanolamine. Electroless copper plating was carried out effectively on the modified films. The catalytic processes for the electroless copper plating in the presence and the absence of SnCl2 sensitization were studied and the optimum activation conditions that give the highest plating rate were determined. The effect of grafting degree on the plating rate is studied. Electroless plating conditions (bath additives, pH and temperature) were optimized. Plating rate was determined gravimetrically and spectrophotometrically at different grafting degrees. The results reveal that plating rate is a function of degree of grafting and increases with increasing grafted vinyl ether of monoethanolamine onto polyethylene. It was found that pH 13 of electroless bath and plating temperature 40°C are the optimal conditions for the plating process. The increasing of grafting degree results in faster plating rate at the same pH and temperature. The surface morphology of the metallized films was investigated using scanning electron microscopy (SEM). The adhesion strength between the metallized layer and grafted polymer was studied using tensile machine. SEM photos and adhesion measurements clarified that uniform and adhered deposits were obtained under optimum conditions.

Alphanumeric LCD infrared control via computer’s parallel port

The present work will explain a method to achieve a remote controlled (via IR LED) alphanumeric Liquid Crystal Display. In modern times, the remote access of different devices has become quite popular, therefore, the aim of this project is to provide a useful tool that will integrate common and easy to access devices. The system includes a C language based user interface, an assembly language code for the AT89C51ED2 microcontroller instructions and some digital electronic circuits needed for the driving and control of both the LCD and the infrared communication, as well as the PC with a parallel port. The interaction of all the devices provides a whole system that can be helpful in different applications, or it can be separated into each one of its different stages to take the best advantage as possible.

Design of boundary-scan testing in CMOS image sensors for industrial applications: internship repor

Tests on printed circuit boards and integrated circuits are widely used in industry,resulting in reduced design time and cost of a project. The functional and connectivity tests in this type of circuits soon began to be a concern for the manufacturers, leading to research for solutions that would allow a reliable, quick, cheap and universal solution. Initially, using test schemes were based on a set of needles that was connected to inputs and outputs of the integrated circuit board (bed-of-nails), to which signals were applied, in order to verify whether the circuit was according to the specifications and could be assembled in the production line. With the development of projects, circuit miniaturization, improvement of the production processes, improvement of the materials used, as well as the increase in the number of circuits, it was necessary to search for another solution. Thus Boundary-Scan Testing was developed which operates on the border of integrated circuits and allows testing the connectivity of the input and the output ports of a circuit. The Boundary-Scan Testing method was converted into a standard, in 1990, by the IEEE organization, being known as the IEEE 1149.1 Standard. Since then a large number of manufacturers have adopted this standard in their products. This master thesis has, as main objective: the design of Boundary-Scan Testing in an image sensor in CMOS technology, analyzing the standard requirements, the process used in the prototype production, developing the design and layout of Boundary-Scan and analyzing obtained results after production. Chapter 1 presents briefly the evolution of testing procedures used in industry, developments and applications of image sensors and the motivation for the use of architecture Boundary-Scan Testing. Chapter 2 explores the fundamentals of Boundary-Scan Testing and image sensors, starting with the Boundary-Scan architecture defined in the Standard, where functional blocks are analyzed. This understanding is necessary to implement the design on an image sensor. It also explains the architecture of image sensors currently used, focusing on sensors with a large number of inputs and outputs.Chapter 3 describes the design of the Boundary-Scan implemented and starts to analyse the design and functions of the prototype, the used software, the designs and simulations of the functional blocks of the Boundary-Scan implemented. Chapter 4 presents the layout process used based on the design developed on chapter 3, describing the software used for this purpose, the planning of the layout location (floorplan) and its dimensions, the layout of individual blocks, checks in terms of layout rules, the comparison with the final design and finally the simulation. Chapter 5 describes how the functional tests were performed to verify the design compliancy with the specifications of Standard IEEE 1149.1. These tests were focused on the application of signals to input and output ports of the produced prototype. Chapter 6 presents the conclusions that were taken throughout the execution of the work.

Metodologia de Verificação Funcional para Circuitos Analógicos

This work proposes a new methodology to verify those analog circuits, providing an automated tools to help the verifiers to have a more truthful result. This work presents the development of new methodology for analog circuits verification. The main goal is to provide a more automated verification process to certify analog circuits functional behavior. The proposed methodology is based on the golden model technique. A verification environment based on this methodology was built and results of a study case based on the validation of an operational amplifier design are offered as a confirmation of its effectiveness. The results had shown that the verification process was more truthful because of the automation provided by the tool developed

Análise do espalhamento espectral em superfícies de estruturas complexas para comunicações móveis

In this work, the transmission line method is explored on the study of the propagation phenomenon in nonhomogeneous walls with finite thickness. It is evaluated the efficiency and applicability of the method, considering materials like gypsum, wood and brick, found in the composition of the structures of walls in question. The results obtained in this work are compared to those available in the literature, for several particular cases. A good agreement is observed, showing that the performed analysis is accurate and efficient in modeling, for instance, the wave propagation through building walls and integrated circuit layers in mobile communication and radar system applications. Later, simulations of resistive sheets devices such as Salisbury screens and Jaumann absorbers and of transmission lines made of metal-insulator-semiconductor (MIS) are made. Thereafter, it is described a study on frequency surface selective structures (FSS). It is proposed the development of devices and microwave integrated circuits (MIC) of such structures, for the accomplishment of experiments. Finally, future works are suggested, for instance, on the development of reflectarrays, frequency selective surfaces with dissimilar elements, and coupled frequency selective surfaces with elements located on different layers

A multisampling time-domain CMOS imager with synchronous readout circuit

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)