963 resultados para WC-CoCr
Resumo:
A bottom-up technique for synthesizing transversely suspended zinc oxide nanowires (ZnO NWs) under a zinc nitrate (Zn(NO 3) 2· 6H 2O) and hexamethylenetetramine (HMTA, (CH 2) 6·N 4) solution within a microfabricated device is reported in this paper. The device consists of a microheater which is used to initially create an oxidized ZnO seed layer. ZnO NWs are then locally synthesized by the microheater and electrodes embedded within the devices are used to drive electric field directed horizontal alignment of the nanowires within the device. The entire process is carried out at low temperature. This approach has the potential to considerably simplify the fabrication and assembly of ZnO nanowires on CMOS compatible substrates, allowing for the chemical synthesis to be carried out under near-ambient conditions by locally defining the conditions for nanowire growth on a silicon reactor chip. © 2012 IEEE.
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An advanced 700V Smart Trench IGBT with monolithically integrated over-voltage and over-current protecting circuits is presented in this paper. The proposed Smart IGBT comprises a sense IGBT, a low voltage lateral n-channel MOSFET (M 1), an avalanche diode (D av), and poly-crystalline Zener diodes (ZD) and resistor (R poly). Mix-mode transient simulations with MEDICI have proven the functionalities of the protecting circuits when the device is operating under abnormal conditions, such as Unclamped Inductive Switching (UIS) and Short Circuit (SC) condition. A Trench IGBT process is used to fabricate this device with total 11 masks including one metal mask only. The characterizations of the fabricated device exhibit the clamping capability of the avalanche diode and voltage pull-down ability of the MOSFET. © 2012 IEEE.
Resumo:
A catalyst-free synthesis of ZnO nanostructures using platinum microheaters under ambient environmental conditions has been developed. Different types of ZnO nanostructures are synthesized from the oxidization of Zn thin film by local heating. The characterization of two shapes of Pt microheaters is investigated and the relationship between the applied power for heat generation and ZnO nanostructure synthesis is investigated by local heating experiments under ambient conditions. Based on the developed heating approach, synthesis area, location, and morphologies of ZnO nanostructures can be controlled through the deposited thickness of Zn layer and applied heating voltages. Furthermore, a connected multiple-structure (Zn-ZnO-Zn) layer is synthesized using combinative multimicroheaters. © 2002-2012 IEEE.
Resumo:
It is commonly believed that visual short-term memory (VSTM) consists of a fixed number of "slots" in which items can be stored. An alternative theory in which memory resource is a continuous quantity distributed over all items seems to be refuted by the appearance of guessing in human responses. Here, we introduce a model in which resource is not only continuous but also variable across items and trials, causing random fluctuations in encoding precision. We tested this model against previous models using two VSTM paradigms and two feature dimensions. Our model accurately accounts for all aspects of the data, including apparent guessing, and outperforms slot models in formal model comparison. At the neural level, variability in precision might correspond to variability in neural population gain and doubly stochastic stimulus representation. Our results suggest that VSTM resource is continuous and variable rather than discrete and fixed and might explain why subjective experience of VSTM is not all or none.
Resumo:
In this paper, we demonstrate an approach for the local synthesis of ZnO nanowires (ZnO NWs) and the potential for such structures to be incorporated into device applications. Three network ZnO NW devices are fabricated on a chip by using a bottom-up synthesis approach. Microheaters (defined by standard semiconductor processing) are used to synthesize the ZnO NWs under a zinc nitrate (Zn(NO3)2·6H2O) and hexamethylenetetramine (HMTA, (CH2)6·N4) solution. By controlling synthesis parameters, varying densities of networked ZnO NWs are locally synthesized on the chip. The fabricated networked ZnO NW devices are then characterized using UV excitation and cyclic voltammetry (CV) experiments to measure their photoresponse and electrochemical properties. The experimental results show that the techniques and material systems presented here have the potential to address interesting device applications using fabrication methods that are fully compatible with standard semiconductor processing. © 2013 IEEE.
Resumo:
Our studies investigated the physico-chemical properties of alkaline phosphatase excreted by D. magna. This cladoceran mainly released alkaline phosphatase, though it also released a small amount of acid phosphatase. The alkaline phosphatase showed a broad pH optimum (8.05-10.0), and had a broad optimum temperature (30-35 degrees C) with a temperature coefficient (Q(10)) of 2.45. The K-m of the enzyme is 0.15 +/- 0.02 mM when p-nitrophenyl phosphate is used as a substrate, and the V-max is 0.43 +/- 0.01 mu M pNP mg(-1) DW h(-1). Even though alkaline phosphatase had been incubated in chloroform saturated with WC medium for 13 days, its activity was 54% that of the original. The enzyme was strongly inactivated by EDTA, and appeared to be zinc dependent. The alkaline phosphatase activity remained constant when D. magna was fed different quantities of Chlorella sp. The sensitivity of D. magna phosphatase activity to phosphate was time-dependent. During the first 16 hrs, the enzyme was insensitive to phosphate addition, after 24 hrs incubation the enzyme became sensitive to phosphate addition.
Resumo:
E2SiO5 thin films were fabricated on Si substrate by reactive magnetron sputtering method with subsequent annealing treatment. The morphology properties of as-deposited films have been studied by scanning electron microscope. The fraction of erbium is estimated to be 23.5 at% based on Rutherford backscattering measurement in as-deposited Er-Si-O film. X-ray diffraction measurement revealed that Er2SiO5 crystalline structure was formed as sample treated at 1100 degrees C for 1 h in O-2 atmosphere. Through proper thermal treatment, the 1.53 mu m Er3+-related emission intensity can be enhanced by a factor of 50 with respect to the sample annealed at 800 degrees C. Analysis of pump-power dependence of Er3+ PL intensity indicated that the upconversion phenomenon could be neglected even under a high photon flux of 10(21) (photons/cm(2)/sec). Temperature-dependent photoluminescence (PL) of Er2SiO5 was studied and showed a weak thermal quenching factor of 2. Highly efficienct photoluminescence of Er2SiO5 films has been demonstrated with Er3+ concentration of 10(22)/cm(3), and it opens a promising way towards future Si-based light source for Si photonics. (C) 2009 Elsevier B.V. All rights reserved.
Resumo:
The idler is separated from the co-propagating pump in a degenerate four-wave mixing (DFWM) with a symmetrical parametric loop mirror (PALM), which is composed of two identical SOAs and a 70 m highly-nonlinear photonic crystal fiber (HN-PCF). The signal and pump are coupled into the symmetrical PALM from different ports, respectively. After the DFWM based wavelength conversion (WC) in the clockwise and anticlockwise, the idler exits from the signal port, while the pump outputs from its input port. Therefore, the pump is effectively suppressed in the idler channel without a high-speed tunable filter. Contrast to a traditional PALM, the DFWM based conversion efficiency is increased greatly, and the functions of the amplification and the WC are integrated in the smart SOA and HN-PCF PALM. (C) 2008 Elsevier B.V. All rights reserved.
Resumo:
This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.
Resumo:
A CMOS voltage-mode multi-valued literal gate is presented. The ballistic electron transport characteristic of nanoscale MOSFETs is smartly used to compactly achieve universal radix-4 literal operations. The proposed literal gates have small numbers of transistors and low power dissipations, which makes them promising for future nanoscale multi-valued circuits. The gates are simulated by HSPICE.
Resumo:
Silicon nitride films were deposited by plasma-enhanced chemical-vapour deposition. The films were then implanted with erbium ions to a concentration of 8 x 10(20) cm(-3). After high temperature annealing, strong visible and infrared photoluminescence (PL) was observed. The visible PL consists mainly of two peaks located at 660 and 750 nm, which are considered to originate from silicon nanocluster (Si-NCs) and Si-NC/SiNx interface states. Raman spectra and HRTEM measurements have been performed to confirm the existence of Si-NCs. The implanted erbium ions are possibly activated by an energy transfer process, leading to a strong 1.54 mu m PL.
Resumo:
A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 x 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 x 16 PE array is fabricated by the 0.18 mu m standard CMOS process. It has a pixel size of 30 mu m x 40 mu m and 8.72 mW power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.
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We study the structural defects in the SiOx film prepared by electron cyclotron resonance plasma chemical vapour deposition and annealing recovery evolution. The photoluminescence property is observed in the as-deposited and annealed samples. [-SiO3](2-) defects are the luminescence centres of the ultraviolet photoluminescence (PL) from the Fourier transform infrared spectroscopy and PL measurements. [-SiO3](2-) is observed by positron annihilation spectroscopy, and this defect can make the S parameters increase. After 1000 degrees C annealing, [-SiO3](2-) defects still exist in the films.
Resumo:
This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.