935 resultados para Priority queue


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A queue manager (QM) is a core traffic management (TM) function used to provide per-flow queuing in access andmetro networks; however current designs have limited scalability. An on-demand QM (OD-QM) which is part of a new modular field-programmable gate-array (FPGA)-based TM is presented that dynamically maps active flows to the available physical resources; its scalability is derived from exploiting the observation that there are only a few hundred active flows in a high speed network. Simulations with real traffic show that it is a scalable, cost-effective approach that enhances per-flow queuing performance, thereby allowing per-flow QM without the need for extra external memory at speeds up to 10 Gbps. It utilizes 2.3%–16.3% of a Xilinx XC5VSX50t FPGA and works at 111 MHz.

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We investigate dynamic posture control and working memory (NBack) retest practice in young and older adults, focusing on older adults' potential for improvement in the component tasks but more importantly in dual-task performance. Participants performed the 2 tasks in 11 sessions under single- and dual-task conditions. Posture improvement was observed with retest practice for both groups. Increase in cognitive load after initial practice led to greater dual-task costs in both tasks in older adults and higher costs in memory in young adults. With continued practice, costs were reduced by both groups; however, the 2 groups focused improvement on different tasks: Older adults focused on posture but young adults on cognition. These results emphasize older adults' potential for improvement in dual-task performance and their flexibility to utilize the practice gains in posture to optimize cognitive performance.

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The use of efficient synchronization mechanisms is crucial for implementing fine grained parallel programs on modern shared cache multi-core architectures. In this paper we study this problem by considering Single-Producer/Single- Consumer (SPSC) coordination using unbounded queues. A novel unbounded SPSC algorithm capable of reducing the row synchronization latency and speeding up Producer-Consumer coordination is presented. The algorithm has been extensively tested on a shared-cache multi-core platform and a sketch proof of correctness is presented. The queues proposed have been used as basic building blocks to implement the FastFlow parallel framework, which has been demonstrated to offer very good performance for fine-grain parallel applications. © 2012 Springer-Verlag.

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The temporal priority principle states that all causes must precede their effects. It is widely assumed that children's causal reasoning is guided by this principle from early in development. However, the empirical studies that have examined children's use of the principle, most of which were conducted some decades ago, in fact show inconsistent findings. Some researchers have argued that 3-year-olds reliably use this principle, whereas others have suggested that it is not until 5 years that children properly grasp the inviolability of the principle. To examine this issue, 100 children, 50 three-year-olds, and 50 four-year-olds, took part in a study in which they had to judge which of two causes yielded an effect. In the task, children saw one event (A), an effect (E), and then another event (B). The events A and B involved the rolling of balls down runways, and the effect E was a Jack-in-a-box popping up. The extent to which E left a visible trace was also varied, because comparisons across previous studies suggested that this may affect performance. As a group, 3- and 4-year-olds performed at above-chance levels, but performance improved with age. The nature of the effect did not have a significant impact on performance. Although some previous studies suggested that 3-year-olds may be more likely to choose B rather than A as a cause due to a recency effect, we found no evidence of this pattern of performance in the younger group. Potential explanations of the age-related improvement in performance are discussed. © 2013 Desmet.