Analysis of scoliosis trunk deformities using ICA

This paper describes a method for analyzing scoliosis trunk deformities using Independent Component Analysis (ICA). Our hypothesis is that ICA can capture the scoliosis deformities visible on the trunk. Unlike Principal Component Analysis (PCA), ICA gives local shape variation and assumes that the data distribution is not normal. 3D torso images of 56 subjects including 28 patients with adolescent idiopathic scoliosis and 28 healthy subjects are analyzed using ICA. First, we remark that the independent components capture the local scoliosis deformities as the shoulder variation, the scapula asymmetry and the waist deformation. Second, we note that the different scoliosis curve types are characterized by different combinations of specific independent components.

Cap mòbil amb tecnologia led RGBW controlat per DMX

Disseny tant a nivell de hardware com de software d’un cap mòbil amb tecnologia led RGBW controlat pel protocol DMX512. Aquest projecte es limita al disseny i a la realització de tots els elements de software i hardware necessaris per crear un prototipus de cap mòbil que pugui ser controlat mitjançant el protocol DMX. Per tant, està encarat completament cap a la vessant electrònica i de programació sense fer referència als materials i elements constructius utilitzats o sobre el disseny i estètica del producte

La travesía obsoleta: la indefensión del consumidor

La obsolescencia programada es el deseo de tener algo un poco más nuevo, un poco mejor, un poco más rápido de lo necesario. El texto estudia este fenómeno a la luz del Estatuto del Consumidor – Ley 1480 de 2011 para determinar si el consumidor colombiano está suficientemente protegido con él.

Big and little Meccano

The emergence of the mechanical bond during the past 25 years is giving chemistry a fillip in more ways than one. While its arrival on the scene is already impacting materials science and molecular nanotechnology, it is providing a new lease of life to chemical synthesis where mechanical bond formation Occurs as a consequence of the all-important templation Orchestrated by molecular recognition and self-assembly. The way in which covalent bond formation activates noncovalent bonding interactions, switching on molecular recognition that leads to self-assembly, and the template-directed synthesis of mechanically interlocked molecules-of which the so-called catenanes and rotaxanes may be regarded as the prototypes-has introduced a level of integration into chemical synthesis that has not previously been attained jointly at the supramolecular and molecular levels. The challenge now is to carry this I vel of integration during molecular synthesis beyond relatively small molecules into the realms of precisely functionalized extended molecular Structures and superstructures that perform functions in a collective manner as the key sources of instruction, activation, and performance in multi-component integrated Circuits and devices. These forays into organic chemistry by a scientific nomad are traced through thick and thin from the Athens of the North to the Windy City by Lake Michigan with interludes on the edge of the Canadian Shield beside Lake Ontario, in the Socialist Republic of South Yorkshire, on the Plains of Cheshire beside the Wirral, in the Midlands in the Heartland of Albion, and in the City of Angels beside the Peaceful Sea. (C) 2008 Elsevier Ltd. All rights reserved.

Optimization of electroless copper plating on polyethylene films modified by surface grafting of vinyl ether of monoethanolamine

Metallized plastics have recently received significant interest for their useful applications in electronic devices such as for integrated circuits, packaging, printed circuits and sensor applications. In this work the metallized films were developed by electroless copper plating of polyethylene films grafted with vinyl ether of monoethanoleamine. There are several techniques for metal deposition on surface of polymers such as evaporation, sputtering, electroless plating and electrolysis. In this work the metallized films were developed by electroless copper plating of polyethylene films grafted with vinyl ether of monoethanoleamine. Polyethylene films were subjected to gamma-radiation induced surface graft copolymerization with vinyl ether of monoethanolamine. Electroless copper plating was carried out effectively on the modified films. The catalytic processes for the electroless copper plating in the presence and the absence of SnCl2 sensitization were studied and the optimum activation conditions that give the highest plating rate were determined. The effect of grafting degree on the plating rate is studied. Electroless plating conditions (bath additives, pH and temperature) were optimized. Plating rate was determined gravimetrically and spectrophotometrically at different grafting degrees. The results reveal that plating rate is a function of degree of grafting and increases with increasing grafted vinyl ether of monoethanolamine onto polyethylene. It was found that pH 13 of electroless bath and plating temperature 40°C are the optimal conditions for the plating process. The increasing of grafting degree results in faster plating rate at the same pH and temperature. The surface morphology of the metallized films was investigated using scanning electron microscopy (SEM). The adhesion strength between the metallized layer and grafted polymer was studied using tensile machine. SEM photos and adhesion measurements clarified that uniform and adhered deposits were obtained under optimum conditions.

Systematic and random errors between collocated satellite ice water path observations

There remains large disagreement between ice-water path (IWP) in observational data sets, largely because the sensors observe different parts of the ice particle size distribution. A detailed comparison of retrieved IWP from satellite observations in the Tropics (!30 " latitude) in 2007 was made using collocated measurements. The radio detection and ranging(radar)/light detection and ranging (lidar) (DARDAR) IWP data set, based on combined radar/lidar measurements, is used as a reference because it provides arguably the best estimate of the total column IWP. For each data set, usable IWP dynamic ranges are inferred from this comparison. IWP retrievals based on solar reflectance measurements, in the moderate resolution imaging spectroradiometer (MODIS), advanced very high resolution radiometer–based Climate Monitoring Satellite Applications Facility (CMSAF), and Pathfinder Atmospheres-Extended (PATMOS-x) datasets, were found to be correlated with DARDAR over a large IWP range (~20–7000 g m -2 ). The random errors of the collocated data sets have a close to lognormal distribution, and the combined random error of MODIS and DARDAR is less than a factor of 2, which also sets the upper limit for MODIS alone. In the same way, the upper limit for the random error of all considered data sets is determined. Data sets based on passive microwave measurements, microwave surface and precipitation products system (MSPPS), microwave integrated retrieval system (MiRS), and collocated microwave only (CMO), are largely correlated with DARDAR for IWP values larger than approximately 700 g m -2 . The combined uncertainty between these data sets and DARDAR in this range is slightly less MODIS-DARDAR, but the systematic bias is nearly an order of magnitude.

Design of boundary-scan testing in CMOS image sensors for industrial applications: internship repor

Tests on printed circuit boards and integrated circuits are widely used in industry,resulting in reduced design time and cost of a project. The functional and connectivity tests in this type of circuits soon began to be a concern for the manufacturers, leading to research for solutions that would allow a reliable, quick, cheap and universal solution. Initially, using test schemes were based on a set of needles that was connected to inputs and outputs of the integrated circuit board (bed-of-nails), to which signals were applied, in order to verify whether the circuit was according to the specifications and could be assembled in the production line. With the development of projects, circuit miniaturization, improvement of the production processes, improvement of the materials used, as well as the increase in the number of circuits, it was necessary to search for another solution. Thus Boundary-Scan Testing was developed which operates on the border of integrated circuits and allows testing the connectivity of the input and the output ports of a circuit. The Boundary-Scan Testing method was converted into a standard, in 1990, by the IEEE organization, being known as the IEEE 1149.1 Standard. Since then a large number of manufacturers have adopted this standard in their products. This master thesis has, as main objective: the design of Boundary-Scan Testing in an image sensor in CMOS technology, analyzing the standard requirements, the process used in the prototype production, developing the design and layout of Boundary-Scan and analyzing obtained results after production. Chapter 1 presents briefly the evolution of testing procedures used in industry, developments and applications of image sensors and the motivation for the use of architecture Boundary-Scan Testing. Chapter 2 explores the fundamentals of Boundary-Scan Testing and image sensors, starting with the Boundary-Scan architecture defined in the Standard, where functional blocks are analyzed. This understanding is necessary to implement the design on an image sensor. It also explains the architecture of image sensors currently used, focusing on sensors with a large number of inputs and outputs.Chapter 3 describes the design of the Boundary-Scan implemented and starts to analyse the design and functions of the prototype, the used software, the designs and simulations of the functional blocks of the Boundary-Scan implemented. Chapter 4 presents the layout process used based on the design developed on chapter 3, describing the software used for this purpose, the planning of the layout location (floorplan) and its dimensions, the layout of individual blocks, checks in terms of layout rules, the comparison with the final design and finally the simulation. Chapter 5 describes how the functional tests were performed to verify the design compliancy with the specifications of Standard IEEE 1149.1. These tests were focused on the application of signals to input and output ports of the produced prototype. Chapter 6 presents the conclusions that were taken throughout the execution of the work.

Metodologia de Verificação Funcional para Circuitos Analógicos

This work proposes a new methodology to verify those analog circuits, providing an automated tools to help the verifiers to have a more truthful result. This work presents the development of new methodology for analog circuits verification. The main goal is to provide a more automated verification process to certify analog circuits functional behavior. The proposed methodology is based on the golden model technique. A verification environment based on this methodology was built and results of a study case based on the validation of an operational amplifier design are offered as a confirmation of its effectiveness. The results had shown that the verification process was more truthful because of the automation provided by the tool developed

Caracterização de circuitos planares de micro-ondas pelo método iterativo das ondas

The planar circuits are structures that increasingly attracting the attention of researchers, due the good performance and capacity to integrate with other devices, in the prototyping of systems for transmitting and receiving signals in the microwave range. In this context, the study and development of new techniques for analysis of these devices have significantly contributed in the design of structures with excellent performance and high reliability. In this work, the full-wave method based on the concept of electromagnetic waves and the principle of reflection and transmission of waves at an interface, Wave Concept Iterative Procedure (WCIP), or iterative method of waves is described as a tool with high precision study microwave planar circuits. The proposed method is applied to the characterization of planar filters, microstrip antennas and frequency selective surfaces. Prototype devices were built and the experimental results confirmed the proposed mathematical model. The results were also compared with simulated results by Ansoft HFSS, observing a good agreement between them.

A multisampling time-domain CMOS imager with synchronous readout circuit

Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)

Flexural Test on Recycled Polystyrene

In socio-environmental scenario increased the nature resources concern beyond products and subproducts reuse. Recycling is the approach for a material or energy reintroducing in productive system. This method allows the reduction of garbage volume dumped in environment, saving energy and decreasing the requirement of natural resources use. In general, the ending of expanded polystyrene is deposited sanitary landfills or garbage dumps without control that take large volume and spreads easily by aeolian action, with consequently environmental pollution, however, the recycling avoids their misuse and the obtainment from petroleum is reduced. This work recycled expanded polystyrene via merger and/or dissolution by solvents for the production of integrated circuits boards. The obtained material was characterized in flexural mode according to ASTM D 790 and results were compared with phenolite, traditionally used. Specimens fractures were observed by electronic microscopy scanning in order to establish patterns. Expanded Polyestirene recycled as well as phenolite were also thermo analyzed by TGA and DSC. The method using dissolution produced very brittle materials. The method using merger showed no voids formation nor increased the brittleness of the material. The recycled polystyrene presented a strength value significantly lower than that for the phenolite. (C) 2011 Published by Elsevier Ltd. Selection and peer-review under responsibility of ICM11

A current-mode based Field-Programmable Analog Array for signal processing applications

This paper presents a new approach to develop Field Programmable Analog Arrays (FPAAs),(1) which avoids excessive number of programming elements in the signal path, thus enhancing the performance. The paper also introduces a novel FPAA architecture, devoid of the conventional switching and connection modules. The proposed FPAA is based on simple current mode sub-circuits. An uncompounded methodology has been employed for the programming of the Configurable Analog Cell (CAC). Current mode approach has enabled the operation of the FPAA presented here, over almost three decades of frequency range. We have demonstrated the feasibility of the FPAA by implementing some signal processing functions.

Low voltage four-quadrant current multiplier: an improved topology for n-well CMOS process

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Avaliação da execução de aplicações orientadas à dados na arquitetura de redes em chip IPNoSys

The increasing complexity of integrated circuits has boosted the development of communications architectures like Networks-on-Chip (NoCs), as an architecture; alternative for interconnection of Systems-on-Chip (SoC). Networks-on-Chip complain for component reuse, parallelism and scalability, enhancing reusability in projects of dedicated applications. In the literature, lots of proposals have been made, suggesting different configurations for networks-on-chip architectures. Among all networks-on-chip considered, the architecture of IPNoSys is a non conventional one, since it allows the execution of operations, while the communication process is performed. This study aims to evaluate the execution of data-flow based applications on IPNoSys, focusing on their adaptation against the design constraints. Data-flow based applications are characterized by the flowing of continuous stream of data, on which operations are executed. We expect that these type of applications can be improved when running on IPNoSys, because they have a programming model similar to the execution model of this network. By observing the behavior of these applications when running on IPNoSys, were performed changes in the execution model of the network IPNoSys, allowing the implementation of an instruction level parallelism. For these purposes, analysis of the implementations of dataflow applications were performed and compared

Settling analysis of MOS regulated current mirrors applied to micropower D/A converters

This paper provides an insight to the trade-off between settling time and power consumption in regulated current mirrors as building parts in micropower current-switching D/A converters. The regulation-loop frequency characteristic is obtained and difficulties to impose a dominant-pole condition to the resulting 2nd-order system are evaluated. Raising pole frequencies in micropower circuits, while meeting consumption requirements, is basically limited by parasitic capacitances. For such cases, an alternative is to impose a twin-pole condition in which design constraints are somewhat relieved and settling slightly improved. Relationships between pole frequencies, transistor geometry and bias are established and design guidelines for regulated current mirrors founded. By placing loop-transistors in either weak or strong inversion, small (W/L) ratios are allowed and stray capacitances reduced. Simulated waveforms suggest a good agreement with theory. The proposed approach applied to the design of a micropower current-mode D/A converter improves both simulated and experimental settling performance.