A bang-bang PLL employing dynamic gain control for low jitter and fast lock times

Bang-bang phase detector based PLLs are simple to design, suffer no systematic phase error, and can run at the highest speed a process can make a working flip-flop. For these reasons designers are employing them in the design of very high speed Clock Data Recovery (CDR) architectures. The major drawback of this class of PLL is the inherent jitter due to quantized phase and frequency corrections. Reducing loop gain can proportionally improve jitter performance, but also reduces locking time and pull-in range. This paper presents a novel PLL design that dynamically scales its gain in order to achieve fast lock times while improving fitter performance in lock. Under certain circumstances the design also demonstrates improved capture range. This paper also analyses the behaviour of a bang-bang type PLL when far from lock, and demonstrates that the pull-in range is proportional to the square root of the PLL loop gain.

A class of self-stabilizing MCA learning algorithms

In this letter, we propose a class of self-stabilizing learning algorithms for minor component analysis (MCA), which includes a few well-known MCA learning algorithms. Self-stabilizing means that the sign of the weight vector length change is independent of the presented input vector. For these algorithms, rigorous global convergence proof is given and the convergence rate is also discussed. By combining the positive properties of these algorithms, a new learning algorithm is proposed which can improve the performance. Simulations are employed to confirm our theoretical results.

The status of investigations into the use of continued fractions for computer hardware /

Bibliography: p. 29.

Parallelization of SAT on Reconfigurable Hardware

Quoique tr��s difficile �� r��soudre, le probl��me de satisfiabilit�� Bool��enne (SAT) est fr��quemment utilis�� lors de la mod��lisation d���applications industrielles. �� cet effet, les deux derni��res d��cennies ont vu une progression fulgurante des outils con��us pour trouver des solutions �� ce probl��me NP-complet. Deux grandes avenues g��n��rales ont ��t�� explor��es afin de produire ces outils, notamment l���approche logicielle et mat��rielle. Afin de raffiner et am��liorer ces solveurs, de nombreuses techniques et heuristiques ont ��t�� propos��es par la communaut�� de recherche. Le but final de ces outils a ��t�� de r��soudre des probl��mes de taille industrielle, ce qui a ��t�� plus ou moins accompli par les solveurs de nature logicielle. Initialement, le but de l���utilisation du mat��riel reconfigurable a ��t�� de produire des solveurs pouvant trouver des solutions plus rapidement que leurs homologues logiciels. Cependant, le niveau de sophistication de ces derniers a augment�� de telle mani��re qu���ils restent le meilleur choix pour r��soudre SAT. Toutefois, les solveurs modernes logiciels n���arrivent toujours pas a trouver des solutions de mani��re efficace �� certaines instances SAT. Le but principal de ce m��moire est d���explorer la r��solution du probl��me SAT dans le contexte du mat��riel reconfigurable en vue de caract��riser les ingr��dients n��cessaires d���un solveur SAT efficace qui puise sa puissance de calcul dans le parall��lisme conf��r�� par une plateforme FPGA. Le prototype parall��le impl��ment�� dans ce travail est capable de se mesurer, en termes de vitesse d���ex��cution �� d���autres solveurs (mat��riels et logiciels), et ce sans utiliser aucune heuristique. Nous montrons donc que notre approche mat��rielle pr��sente une option prometteuse vers la r��solution d���instances industrielles larges qui sont difficilement abord��es par une approche logicielle.

Regelbasiertes Reasoning auf massiv paralleler Hardware

Eine wesentliche Funktionalit��t bei der Verwendung semantischer Technologien besteht in dem als Reasoning bezeichneten Prozess des Ableitens von impliziten Fakten aus einer explizit gegebenen Wissensbasis. Der Vorgang des Reasonings stellt vor dem Hintergrund der stetig wachsenden Menge an (semantischen) Informationen zunehmend eine Herausforderung in Bezug auf die notwendigen Ressourcen sowie der Ausf��hrungsgeschwindigkeit dar. Um diesen Herausforderungen zu begegnen, adressiert die vorliegende Arbeit das Reasoning durch eine massive Parallelisierung der zugrunde liegenden Algorithmen und der Einf��hrung von Konzepten f��r eine ressourceneffiziente Ausf��hrung. Diese Ziele werden unter Ber��cksichtigung der Verwendung eines regelbasierten Systems verfolgt, dass im Gegensatz zur Implementierung einer festen Semantik die Definition der anzuwendenden Ableitungsregeln w��hrend der Laufzeit erlaubt und so eine gr����ere Flexibilit��t bei der Nutzung des Systems bietet. Ausgehend von einer Betrachtung der Grundlagen des Reasonings und den verwandten Arbeiten aus den Bereichen des parallelen sowie des regelbasierten Reasonings werden zun��chst die Funktionsweise von Production Systems sowie die dazu bereits existierenden Ans��tze f��r die Optimierung und im Speziellen der Parallelisierung betrachtet. Production Systems beschreiben die grundlegende Funktionalit��t der regelbasierten Verarbeitung und sind somit auch die Ausgangsbasis f��r den RETE-Algorithmus, der zur Erreichung der Zielsetzung der vorliegenden Arbeit parallelisiert und f��r die Ausf��hrung auf Grafikprozessoren (GPUs) vorbereitet wird. Im Gegensatz zu bestehenden Ans��tzen unterscheidet sich die Parallelisierung insbesondere durch die gew��hlte Granularit��t, die nicht durch die anzuwendenden Regeln, sondern von den Eingabedaten bestimmt wird und sich damit an der Zielarchitektur orientiert. Aufbauend auf dem Konzept der parallelen Ausf��hrung des RETE-Algorithmus werden Methoden der Partitionierung und Verteilung der Arbeitslast eingef��hrt, die zusammen mit Konzepten der Datenkomprimierung sowie der Verteilung von Daten zwischen Haupt- und Festplattenspeicher ein Reasoning ��ber Datens��tze mit mehreren Milliarden Fakten auf einzelnen Rechnern erlauben. Eine Evaluation der eingef��hrten Konzepte durch eine prototypische Implementierung zeigt f��r die adressierten leichtgewichtigen Ontologiesprachen einerseits die M��glichkeit des Reasonings ��ber eine Milliarde Fakten auf einem Laptop, was durch die Reduzierung des Speicherbedarfs um rund 90% erm��glicht wird. Andererseits kann der dabei erzielte Durchsatz mit aktuellen State of the Art Reasonern verglichen werden, die eine Vielzahl an Rechnern in einem Cluster verwenden.

Memory Hierarchy Hardware-Software Co-design in Embedded Systems

The memory hierarchy is the main bottleneck in modern computer systems as the gap between the speed of the processor and the memory continues to grow larger. The situation in embedded systems is even worse. The memory hierarchy consumes a large amount of chip area and energy, which are precious resources in embedded systems. Moreover, embedded systems have multiple design objectives such as performance, energy consumption, and area, etc. Customizing the memory hierarchy for specific applications is a very important way to take full advantage of limited resources to maximize the performance. However, the traditional custom memory hierarchy design methodologies are phase-ordered. They separate the application optimization from the memory hierarchy architecture design, which tend to result in local-optimal solutions. In traditional Hardware-Software co-design methodologies, much of the work has focused on utilizing reconfigurable logic to partition the computation. However, utilizing reconfigurable logic to perform the memory hierarchy design is seldom addressed. In this paper, we propose a new framework for designing memory hierarchy for embedded systems. The framework will take advantage of the flexible reconfigurable logic to customize the memory hierarchy for specific applications. It combines the application optimization and memory hierarchy design together to obtain a global-optimal solution. Using the framework, we performed a case study to design a new software-controlled instruction memory that showed promising potential.

A petri net based timing model for hardware/software co-design of digital systems

We have recently proposed an extension to Petri nets in order to be able to directly deal with all aspects of embedded digital systems. This extension is meant to be used as an internal model of our co-design environment. After analyzing relevant related work, and presenting a short introduction to our extension as a background material, we describe the details of the timing model we use in our approach, which is mainly based in Merlin's time model. We conclude the paper by discussing an example of its usage. �� 2004 IEEE.

3D Face Reconstruction from 2D Pictures: First Results of a Web-Based Computer Aided System for Aesthetic Procedures

The human face is a vital component of our identity and many people undergo medical aesthetics procedures in order to achieve an ideal or desired look. However, communication between physician and patient is fundamental to understand the patient���s wishes and to achieve the desired results. To date, most plastic surgeons rely on either ���free hand��� 2D drawings on picture printouts or computerized picture morphing. Alternatively, hardware dependent solutions allow facial shapes to be created and planned in 3D, but they are usually expensive or complex to handle. To offer a simple and hardware independent solution, we propose a web-based application that uses 3 standard 2D pictures to create a 3D representation of the patient���s face on which facial aesthetic procedures such as filling, skin clearing or rejuvenation, and rhinoplasty are planned in 3D. The proposed application couples a set of well-established methods together in a novel manner to optimize 3D reconstructions for clinical use. Face reconstructions performed with the application were evaluated by two plastic surgeons and also compared to ground truth data. Results showed the application can provide accurate 3D face representations to be used in clinics (within an average of 2 mm error) in less than 5 min.

Inner-Hair Cells Parameterized-Hardware Implementation for Personalized Auditory Nerve Stimulation

In this paper the hardware implementation of an inner hair cell model is presented. Main features of the design are the use of Meddis��� transduction structure and the methodology for Design with Reusability. Which allows future migration to new hardware and design refinements for speech processing and custom-made hearing aids

Hardware design of a real-time musical system /

Includes bibliographical references.

The hardware design of a cognitive model demonstrator /

"Supported in part by Contract No. U.S. AEC(11-1)1469."

Eidolyzer: a hardware realization of context-guided picture interpretation.

Cover title.

A revised ALGOL 68 hardware representation for ISO-code and EBCDIC,

Includes bibliographical references.

A hardware realization of a decomposition algorithm /

Originally presented as the author's thesis (M.S.)--University of Illinois at Urbana-Champaign, 1971.

Hardware/software interface for the Stereo-matrix display.

Contract US AEC AT(11-1)1469.