990 resultados para CAPACITANCE-VOLTAGE CHARACTERISTICS


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Schottky diodes resulting from an intimate contact of aluminum on electrodeposited poly(3-methylthiopene) were studied by admittance spectroscopy, capacitance-voltage measurements and voltaic and optically-induced current and capacitance transients. The loss tangents show the existence of interface states that can be removed by vacuum annealing. Furthermore, the C-V curves contradict the idea of movement of the dopant ions.

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Electrical measurements have been performed on poly[2-methoxy, 5 ethyl (2' hexyloxy) paraphenylenevinylene] in a pn junction with silicon. These included current-voltage measurements, capacitance-voltage measurements, capacitance-transient spectroscopy, and admittance spectroscopy. The measurements show evidence for large minority-carrier injection into the polymer possibly enabled by interface states for which evidence is also found. The shallow acceptor level depth (0.12 eV) and four deep trap level activation energies (0.30 and 1.0 eV majority-carrier type; 0.48 and 1.3 eV minority-carrier type) are found. Another trap that is visible at room temperature has point-defect nature. (C) 2001 American Institute of Physics.

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Schottky diodes resulting from an intimate contact of aluminum on electro-deposited poly(3-methylthiopene), PMeT, have been studied by admittance spectroscopy, capacitance-voltage and current-voltage measurements, and optically-induced current transients. The loss-tangents show the existence of interface states that can be removed by vacuum annealing, also visible in the transients. Furthermore, the CV curves don't substantiate the idea of movement of the dopant ions.

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Schottky diodes resulting from an intimate contact of aluminum on electrodeposited poly(3-methylthiopene) were studied by admittance spectroscopy, capacitance-voltage measurements and voltaic and optically-induced current and capacitance transients. The loss tangents show the existence of interface states that can be removed by vacuum annealing. Furthermore, the C-V curves contradict the idea of movement of the dopant ions.

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Amorphous semiconductors are important materials as they can be deposited by physical deposition techniques on large areas and even on plastic substrates. Therefore, they are crucial for transistors in large active matrices for imaging and transparent wearable electronics. The most widely applied candidate for amorphous thin film transistors production is Indium Gallium Zinc Oxide (IGZO). It is attracting much interest because of its optical transparency, facile processing by sputtering deposition and notable improved charge carrier mobility with respect to hydrogenated amorphous silicon a-Si:H. Degradation of the device and long-term performance issues have been observed if IGZO thin film transistors are subjected to electrical stress, leading to a modification of IGZO channel properties and subthreshold slope. Therefore, it is of great interest to have a reliable and precise method to study the conduction band tail, and the density of states in amorphous semiconductors. The aim of this thesis is to develop a local technique using Kelvin Probe Force Microscopy to study the evolution of IGZO DOS properties. The work is divided into three main parts. First, solutions to the non-linear Poisson-Boltzmann equation of a metal-insulator-semiconductor junction describing the charge accumulation and its relation to DOS properties are elaborated. Second macroscopic techniques such as capacitance voltage (CV) measurements and photocurrent spectroscopy are applied to obtain a non-local estimate of band-tail DOS properties in thin film transistor samples. The third part of my my thesis is dedicated to the KPFM measurements. By fitting the data to the developed numerical model, important parameters describing the amorphous conduction band tail are obtained. The results are in excellent agreement with the macroscopic characterizations. KPFM result is comparable also with non-local optoelectronic characterizations, such as photocurrent spectroscopy.

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This work looks at the effect on mid-gap interface state defect density estimates for In0.53Ga0.47As semiconductor capacitors when different AC voltage amplitudes are selected for a fixed voltage bias step size (100 mV) during room temperature only electrical characterization. Results are presented for Au/Ni/Al2O3/In0.53Ga0.47As/InP metal–oxide–semiconductor capacitors with (1) n-type and p-type semiconductors, (2) different Al2O3 thicknesses, (3) different In0.53Ga0.47As surface passivation concentrations of ammonium sulphide, and (4) different transfer times to the atomic layer deposition chamber after passivation treatment on the semiconductor surface—thereby demonstrating a cross-section of device characteristics. The authors set out to determine the importance of the AC voltage amplitude selection on the interface state defect density extractions and whether this selection has a combined effect with the oxide capacitance. These capacitors are prototypical of the type of gate oxide material stacks that could form equivalent metal–oxide–semiconductor field-effect transistors beyond the 32 nm technology node. The authors do not attempt to achieve the best scaled equivalent oxide thickness in this work, as our focus is on accurately extracting device properties that will allow the investigation and reduction of interface state defect densities at the high-k/III–V semiconductor interface. The operating voltage for future devices will be reduced, potentially leading to an associated reduction in the AC voltage amplitude, which will force a decrease in the signal-to-noise ratio of electrical responses and could therefore result in less accurate impedance measurements. A concern thus arises regarding the accuracy of the electrical property extractions using such impedance measurements for future devices, particularly in relation to the mid-gap interface state defect density estimated from the conductance method and from the combined high–low frequency capacitance–voltage method. The authors apply a fixed voltage step of 100 mV for all voltage sweep measurements at each AC frequency. Each of these measurements is repeated 15 times for the equidistant AC voltage amplitudes between 10 mV and 150 mV. This provides the desired AC voltage amplitude to step size ratios from 1:10 to 3:2. Our results indicate that, although the selection of the oxide capacitance is important both to the success and accuracy of the extraction method, the mid-gap interface state defect density extractions are not overly sensitive to the AC voltage amplitude employed regardless of what oxide capacitance is used in the extractions, particularly in the range from 50% below the voltage sweep step size to 50% above it. Therefore, the use of larger AC voltage amplitudes in this range to achieve a better signal-to-noise ratio during impedance measurements for future low operating voltage devices will not distort the extracted interface state defect density.

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A new method to extract MOSFET's threshold voltage VT by measurement of the gate-to-substrate capacitance C-gb of the transistor is presented. Unlike existing extraction methods based on I-V data, the measurement of C-gb does not require de drain current to now between drain and source thus eliminating the effects of source and drain series resistance R-S/D, and at the same time, retains a symmetrical potential profile across the channel. Experimental and simulation results on devices with different sizes are presented to justify the proposed method.

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Recent technological developments have created new devices that could improve and simplify the construction of stimulus isolators. HEXFET transistors can switch large currents and hundreds of volts in nanoseconds. The newer opto-isolators can give a pulse rise time of a few nanoseconds, with output compatible with MOSFET devices, in which delays are reduced to nanoseconds. Integrated DC/DC converters are now available. Using these new resources we developed a new electrical stimulus isolator circuit with selectable constant-current and constant-voltage modes, which are precise and easy to construct. The circuit works like a regulated power supply in both modes with output switched to zero or to free mode through an opto-isolator device. The isolator analyses showed good practical performance. The output to ground resistance was 1011 ohms and capacitance 35 picofarads. The rise time and fall time were identical (5 µs) and constant. The selectable voltage or current output mode made it very convenient to use. The current mode, with higher output resistance values in low current ranges, permits intracellular stimulation even with tip resistances close to 100 megaohms. The high compliance of 200 V guarantees the value of the current stimulus. The very low output resistance in the voltage mode made the device highly suitable for extracellular stimulation with low impedance electrodes. Most importantly, these characteristics were achieved with a circuit that was easy to build and modify and assembled with components available in Brazil.

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BiFeO3 (BFO) thin films were fabricated on Pt(111)/Ti/SiO2/Si substrates by using a polymeric precursor solution under appropriate crystallization conditions. The capacitance dependence on voltage is strongly nonlinear, confirming the ferroelectric properties of the films resulting from the domain switching. The leakage current density increases with annealing temperature. The polarization electric field curves could be obtained in BFO films annealed at 500 degrees C, free of secondary phases. X-ray photoelectron spectroscopy spectra of films annealed at 500 degrees C indicated that the oxidation state of Fe was purely 3+, demonstrating that our films possess stable chemical configurations. (c) 2007 American Institute of Physics.

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The purpose of this investigation was to study the source characteristics of a clinical kilo-voltage cone beam CT unit and to develop and validate a virtual source model that could be used for treatment planning purposes.

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We have used capacitance measurements with a 1-microsecond voltage clamp technique to probe electrogenic ion-transporter interactions in giant excised membrane patches. The hydrophobic ion dipicrylamine was used to test model predictions for a simple charge-moving reaction. The voltage and frequency dependencies of the apparent dipicrylamine-induced capacitance, monitored by 1-mV sinusoidal perturbations, correspond to single charges moving across 76% of the membrane field at a rate of 9500 s-1 at 0 mV. For the cardiac Na,K pump, the combined presence of cytoplasmic ATP and sodium induces an increase of apparent membrane capacitance which requires the presence of extracellular sodium. The dependencies of capacitance changes on frequency, voltage, ATP, and sodium verify that phosphorylation enables a slow, 300- to 900-s-1, pump transition (the E1-E2 conformational change), which in turn enables fast, electrogenic, extracellular sodium binding reactions. For the GAT1 (gamma-aminobutyric acid,Na,Cl) cotransporter, expressed in Xenopus oocyte membrane, we find that chloride binding from the cytoplasmic side, and probably sodium binding from the extracellular side, results in a decrease of membrane capacitance monitored with 1- to 50-kHz perturbation frequencies. Evidently, ion binding by the GAT1 transporter suppresses an intrinsic fast charge movement which may originate from a mobility of charged residues of the transporter binding sites. The results demonstrate that fast capacitance measurements can provide new insight into electrogenic processes closely associated with ion binding by membrane transporters.

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"Sponsored by the Air Force Flight Dynamics Laboratory ... under Contract AF 33(615)-1835."

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Includes bibliographical references (p. 49).

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High-volume capacitance is required to buffer the power difference between the input and output ports in single-phase grid-connected photovoltaic inverters, which become an obstacle to high system efficiency and long device lifetime. Furthermore, total harmonic distortion becomes serious when the system runs into low power level. In this study, a comprehensive analysis is introduced for two-stage topology with the consideration of active power, DC-link (DCL) voltage, ripple and capacitance. This study proposed a comprehensive DCL voltage control strategy to minimise the DCL capacitance while maintaining a normal system operation. Furthermore, the proposed control strategy is flexible to be integrated with the pulse-skipping control that significantly improves the power quality at light power conditions. Since the proposed control strategy needs to vary DCL voltage, an active protection scheme is also introduced to prevent any voltage violation across the DCL. The proposed control strategy is evaluated by both simulation and experiments, whose results confirm the system effectiveness.

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The trapezium is often a better approximation for the FinFET cross-section shape, rather than the design-intended rectangle. The frequent width variations along the vertical direction, caused by the etching process that is used for fin definition, may imply in inclined sidewalls and the inclination angles can vary in a significant range. These geometric variations may cause some important changes in the device electrical characteristics. This work analyzes the influence of the FinFET sidewall inclination angle on some relevant parameters for analog design, such as threshold voltage, output conductance, transconductance, intrinsic voltage gain (A V), gate capacitance and unit-gain frequency, through 3D numeric simulation. The intrinsic gain is affected by alterations in transconductance and output conductance. The results show that both parameters depend on the shape, but in different ways. Transconductance depends mainly on the sidewall inclination angle and the fixed average fin width, whereas the output conductance depends mainly on the average fin width and is weakly dependent on the sidewall inclination angle. The simulation results also show that higher voltage gains are obtained for smaller average fin widths with inclination angles that correspond to inverted trapeziums, i.e. for shapes where the channel width is larger at the top than at the transistor base because of the higher attained transconductance. When the channel top is thinner than the base, the transconductance degradation affects the intrinsic voltage gain. The total gate capacitances also present behavior dependent on the sidewall angle, with higher values for inverted trapezium shapes and, as a consequence, lower unit-gain frequencies.