Multi Processor Systems On Chip with Configurable Hardware Acceleration

The evolution of the electronics embedded applications forces electronics systems designers to match their ever increasing requirements. This evolution pushes the computational power of digital signal processing systems, as well as the energy required to accomplish the computations, due to the increasing mobility of such applications. Current approaches used to match these requirements relies on the adoption of application specific signal processors. Such kind of devices exploits powerful accelerators, which are able to match both performance and energy requirements. On the other hand, the too high specificity of such accelerators often results in a lack of flexibility which affects non-recurrent engineering costs, time to market, and market volumes too. The state of the art mainly proposes two solutions to overcome these issues with the ambition of delivering reasonable performance and energy efficiency: reconfigurable computing and multi-processors computing. All of these solutions benefits from the post-fabrication programmability, that definitively results in an increased flexibility. Nevertheless, the gap between these approaches and dedicated hardware is still too high for many application domains, especially when targeting the mobile world. In this scenario, flexible and energy efficient acceleration can be achieved by merging these two computational paradigms, in order to address all the above introduced constraints. This thesis focuses on the exploration of the design and application spectrum of reconfigurable computing, exploited as application specific accelerators for multi-processors systems on chip. More specifically, it introduces a reconfigurable digital signal processor featuring a heterogeneous set of reconfigurable engines, and a homogeneous multi-core system, exploiting three different flavours of reconfigurable and mask-programmable technologies as implementation platform for applications specific accelerators. In this work, the various trade-offs concerning the utilization multi-core platforms and the different configuration technologies are explored, characterizing the design space of the proposed approach in terms of programmability, performance, energy efficiency and manufacturing costs.

Model predictive control in thermal management of multiprocessor systems-on-chip

MultiProcessor Systems-on-Chip (MPSoC) are the core of nowadays and next generation computing platforms. Their relevance in the global market continuously increase, occupying an important role both in everydaylife products (e.g. smartphones, tablets, laptops, cars) and in strategical market sectors as aviation, defense, robotics, medicine. Despite of the incredible performance improvements in the recent years processors manufacturers have had to deal with issues, commonly called “Walls”, that have hindered the processors development. After the famous “Power Wall”, that limited the maximum frequency of a single core and marked the birth of the modern multiprocessors system-on-chip, the “Thermal Wall” and the “Utilization Wall” are the actual key limiter for performance improvements. The former concerns the damaging effects of the high temperature on the chip caused by the large power densities dissipation, whereas the second refers to the impossibility of fully exploiting the computing power of the processor due to the limitations on power and temperature budgets. In this thesis we faced these challenges by developing efficient and reliable solutions able to maximize performance while limiting the maximum temperature below a fixed critical threshold and saving energy. This has been possible by exploiting the Model Predictive Controller (MPC) paradigm that solves an optimization problem subject to constraints in order to find the optimal control decisions for the future interval. A fully-distributedMPC-based thermal controller with a far lower complexity respect to a centralized one has been developed. The control feasibility and interesting properties for the simplification of the control design has been proved by studying a partial differential equation thermal model. Finally, the controller has been efficiently included in more complex control schemes able to minimize energy consumption and deal with mixed-criticalities tasks

Parallel Architectures for Many-Core Systems-On-Chip in Deep Sub-Micron Technology

Despite the several issues faced in the past, the evolutionary trend of silicon has kept its constant pace. Today an ever increasing number of cores is integrated onto the same die. Unfortunately, the extraordinary performance achievable by the many-core paradigm is limited by several factors. Memory bandwidth limitation, combined with inefficient synchronization mechanisms, can severely overcome the potential computation capabilities. Moreover, the huge HW/SW design space requires accurate and flexible tools to perform architectural explorations and validation of design choices. In this thesis we focus on the aforementioned aspects: a flexible and accurate Virtual Platform has been developed, targeting a reference many-core architecture. Such tool has been used to perform architectural explorations, focusing on instruction caching architecture and hybrid HW/SW synchronization mechanism. Beside architectural implications, another issue of embedded systems is considered: energy efficiency. Near Threshold Computing is a key research area in the Ultra-Low-Power domain, as it promises a tenfold improvement in energy efficiency compared to super-threshold operation and it mitigates thermal bottlenecks. The physical implications of modern deep sub-micron technology are severely limiting performance and reliability of modern designs. Reliability becomes a major obstacle when operating in NTC, especially memory operation becomes unreliable and can compromise system correctness. In the present work a novel hybrid memory architecture is devised to overcome reliability issues and at the same time improve energy efficiency by means of aggressive voltage scaling when allowed by workload requirements. Variability is another great drawback of near-threshold operation. The greatly increased sensitivity to threshold voltage variations in today a major concern for electronic devices. We introduce a variation-tolerant extension of the baseline many-core architecture. By means of micro-architectural knobs and a lightweight runtime control unit, the baseline architecture becomes dynamically tolerant to variations.

Die Regulation der Ubiquitinligase CHIP durch das Cochaperon BAG2 im zellulären System und im Kontext der replikativen Seneszenz

Eine funktionierende Proteinqualitätskontrolle ist essenziell für die Vitalität einer Zelle. Das dynamische Gleichgewicht zwischen Proteinfaltung und -degradation wird von molekularen Chaperonen aufrechterhalten, deren Aktivität wiederum durch die Interaktion mit zahlreichen Cochaperonen moduliert wird. Das Cochaperon CHIP ist ein zentraler Faktor in Proteintriage-Entscheidungsprozessen, da es als Ubiquitinligase Chaperonsubstrate dem Abbau zuführt und somit die Chaperonmaschinerie direkt mit den Systemen der Proteindegradation verbindet. Um Polypeptide vor einem vorzeitigen Abbau zu schützen, wird die destruktive Aktivität von CHIP durch weitere Cochaperone reguliert. rnIn dieser Arbeit konnte die Hemmung der Ligaseaktivität von CHIP durch das Cochaperon BAG2 mechanistisch erstmals in einem zellulären System nachgewiesen werden. Dazu wurde die humane IMR-90 Fibroblasten Zelllinie verwendet. Die Ubiquitinierungsaktivität von CHIP wurde anhand von HSP72 als Modell-CHIP-Substrat untersucht. Durch die verringerte Ubiquitinierung, und damit dem reduzierten Abbau von HSP72, regulierte BAG2 dessen intrazelluläre Proteinspiegel, ohne dabei selbst eine Hitzeschockantwort zu induzieren. Überexprimiertes BAG2 wirkte sich trotz stabilisierter HSP72-Spiegel bei einem appliziertem Hitzestresses negativ auf die Zellvitalität aus, vermutlich da BAG2 durch die Inhibition von CHIP-vermittelter Ubiquitinierung massiv in das Gleichgewicht zwischen Substratfaltung und -degradation eingreift.rnDa sich die Mechanismen der Proteinqualitätskontrolle in der Alterung stark verändern und sich den wandelnden Bedingungen in der Zelle anpassen, wurde in einem zweiten Teil dieser Arbeit mit Hilfe des IMR-90 Zellsystems als etabliertes Modell zellulärer Seneszenz analysiert, inwieweit sich die Aktivität und die Regulation von CHIP durch BAG2 in der zellulären Alterung ändern. In seneszenten Zellen war HSP72 erheblich weniger ubiquitiniert als in jungen Fibroblasten, was auf eine reduzierte CHIP-Aktivität hinweist. Diese blieb jedoch durch BAG2 weiterhin modulierbar. Die Funktion von BAG2 als Inhibitor der Ubiquitinligase CHIP blieb demnach in seneszenten Zellen bestehen. In gealterten Fibroblasten regulierte BAG2 außerdem die Proteinspiegel des CHIP-Substrates und Seneszenzinitiators p53, was BAG2 eine mögliche Rolle in der Etablierung des Seneszenz-Phänotyps zuspricht. Weiterhin unterlagen die Proteinspiegel der beiden funktionell redundanten CHIP-Modulatoren BAG2 und HSPBP1 in der zellulären Alterung einer reziproken Regulation. In gealterten Mäusen trat die gegenläufige Veränderung der beiden Cochaperone gewebsspezifisch in der Lunge auf. Außerdem waren die BAG2-Proteinspiegel im Hippocampus gealterter Tiere signifikant erhöht.rnZusammenfassend konnte anhand der erzielten Ergebnisse die Funktion von BAG2 als Inhibitor von CHIP im zellulären System bestätigt werden. Außerdem durchlaufen die Aktivität und die Regulation von CHIP einen seneszenzspezifischen Adaptationsprozess, welcher für die Erhaltung der Proteostase in der Alterung relevant sein könnte und in welchem die Funktion von BAG2 als CHIP-Modulator möglicherweise eine wichtige Rolle spielt.rnZukünftige Studien könnten die komplexen Mechanismen weiterführend aufklären, mit denen CHIP-Aktivität reguliert wird. Dies kann helfen, der altersbedingten Abnahme an proteostatischer Kontrolle entgegenzuwirken und aberrante Proteinaggregation in altersassoziierten Erkrankungen vorzubeugen.rn

Implementazione dell'algoritmo filtered back-projection (FBP) per architetture low-power di tipo systems-on-chip

Il presente lavoro di tesi, svolto presso i laboratori dell'X-ray Imaging Group del Dipartimento di Fisica e Astronomia dell'Università di Bologna e all'interno del progetto della V Commissione Scientifica Nazionale dell'INFN, COSA (Computing on SoC Architectures), ha come obiettivo il porting e l’analisi di un codice di ricostruzione tomografica su architetture GPU installate su System-On-Chip low-power, al fine di sviluppare un metodo portatile, economico e relativamente veloce. Dall'analisi computazionale sono state sviluppate tre diverse versioni del porting in CUDA C: nella prima ci si è limitati a trasporre la parte più onerosa del calcolo sulla scheda grafica, nella seconda si sfrutta la velocità del calcolo matriciale propria del coprocessore (facendo coincidere ogni pixel con una singola unità di calcolo parallelo), mentre la terza è un miglioramento della precedente versione ottimizzata ulteriormente. La terza versione è quella definitiva scelta perché è la più performante sia dal punto di vista del tempo di ricostruzione della singola slice sia a livello di risparmio energetico. Il porting sviluppato è stato confrontato con altre due parallelizzazioni in OpenMP ed MPI. Si è studiato quindi, sia su cluster HPC, sia su cluster SoC low-power (utilizzando in particolare la scheda quad-core Tegra K1), l’efficienza di ogni paradigma in funzione della velocità di calcolo e dell’energia impiegata. La soluzione da noi proposta prevede la combinazione del porting in OpenMP e di quello in CUDA C. Tre core CPU vengono riservati per l'esecuzione del codice in OpenMP, il quarto per gestire la GPU usando il porting in CUDA C. Questa doppia parallelizzazione ha la massima efficienza in funzione della potenza e dell’energia, mentre il cluster HPC ha la massima efficienza in velocità di calcolo. Il metodo proposto quindi permetterebbe di sfruttare quasi completamente le potenzialità della CPU e GPU con un costo molto contenuto. Una possibile ottimizzazione futura potrebbe prevedere la ricostruzione di due slice contemporaneamente sulla GPU, raddoppiando circa la velocità totale e sfruttando al meglio l’hardware. Questo studio ha dato risultati molto soddisfacenti, infatti, è possibile con solo tre schede TK1 eguagliare e forse a superare, in seguito, la potenza di calcolo di un server tradizionale con il vantaggio aggiunto di avere un sistema portatile, a basso consumo e costo. Questa ricerca si va a porre nell’ambito del computing come uno tra i primi studi effettivi su architetture SoC low-power e sul loro impiego in ambito scientifico, con risultati molto promettenti.

Surface-acoustic-wave counterflow micropumps for on-chip liquid motion control in two-dimensional microchannel arrays

Fully controlled liquid injection and flow in hydrophobic polydimethylsiloxane (PDMS) two-dimensional microchannel arrays based on on-chip integrated, low-voltage-driven micropumps are demonstrated. Our architecture exploits the surface-acoustic-wave (SAW) induced counterflow mechanism and the effect of nebulization anisotropies at crossing areas owing to lateral propagating SAWs. We show that by selectively exciting single or multiple SAWs, fluids can be drawn from their reservoirs and moved towards selected positions of a microchannel grid. Splitting of the main liquid flow is also demonstrated by exploiting multiple SAW beams. As a demonstrator, we show simultaneous filling of two orthogonal microchannels. The present results show that SAW micropumps are good candidates for truly integrated on-chip fluidic networks allowing liquid control in arbitrarily shaped two-dimensional microchannel arrays.

Lung on Chip: In vitro HGF effects on injured alveolar A549 epithelial cells in microfluidic system

Microfluidic systems have become competitive tools in the invitro modelling of diseases and promising alternatives to animal studies. They allow obtaining more invivo like conditions for cellular assays. Research in idiopathic pulmonary fibrosis could benefit from this novel methodological approach to understand the pathophysiology of the disease & develop efficient therapies. The use of hepatocyte growth factor (HGF) for alveolar reepithelisation is a promising approach. In this study, we show a new microfluidic system to analyse the effects of HGF on injured alveolar epithelial cells. Microfluidic systems in polydimethylsiloxane were fabricated by soft lithography. The alveolar A549 epithelial cells (10,000 cells) were seeded and studied in these microfluidic systems with media perfusion (1μl/30min). Injury tests were made on the cells by the perfusion with media containing H2O2 or bleomycin. The degree of injury was then assessed by a metabolic and an apoptotic assays. Wound assays were also performed with a central laminar flow of trypsin. Monitoring of wound closure with HGF vs control media was assessed. The alveolar A549 epithelial cells grew and proliferated in the microfluidic system. In the wound closure assay, the degree of wound closure after 5 hours was (53.3±1.3%) with HGF compared to (9.8±2.4%) without HGF (P <0.001). We present a novel microfluidic model that allows culture, injury and wounding of A549 epithelial cells and represents the first step towards the development of an invitro reconstitution of the alveolar-capillary interface. We were also able to confirm that HGF increased alveolar epithelial repair in this system.

Lung on a chip: Co-culture of alveolar epithelial cells and bone marrow derived stromal stem cells in a microfluidic system

Background: Microfluidics system are novel tools to study cell-cell interactions in vitro. This project focuses on the development of a new microfluidic device to co-culture alveolar epithelial cells and mesenchymal stem cells to study cellular interactions involved in healing the injured alveolar epithelium. Methods: Microfluidic systems in polydimethylsiloxane were fabricated by soft lithography. The alveolar A549 epithelial cells were seeded and injury tests were made on the cells by perfusion with media containing H2O2 or bleomycin during 6 or 18hrs. Rat Bone marrow derived stromal cells (BMSC) were then introduced into the system and cell-cell interaction was studied over 24 hrs. Results: A successful co-culture of A549 alveolar epithelial cells and BMS was achieved in the microfluidic system. The seeded alveolar epithelial cells and BMSC adhered to the bottom surface of the microfluidic device and proliferated under constant perfusion. Epithelial injury to mimic mechanisms seen in idiopathic pulmonary fibrosis was induced in the microchannels by perfusing with H2O2 or bleomycin. Migration of BMSC towards the injured epithelium was observed as well as cell-cell interaction between the two cell types was also seen. Conclusion: We demonstrate a novel microfluidic device aimed at showing interactions between different cell types on the basis of a changing microenvironment. Also we were able to confirm interaction between injured alvolar epithelium and BMSC, and showed that BMSC try to heal the injured epitelium.

On-chip non-invasive and label-free cell discrimination by impedance spectroscopy

OBJECTIVES: Many flow-cytometric cell characterization methods require costly markers and colour reagents. We present here a novel device for cell discrimination based on impedance measurement of electrical cell properties in a microfluidic chip, without the need of extensive sample preparation steps and the requirement of labelling dyes. MATERIALS AND METHODS, RESULTS: We demonstrate that in-flow single cell measurements in our microchip allow for discrimination of various cell line types, such as undifferentiated mouse fibroblasts 3T3-L1 and adipocytes on the one hand, or human monocytes and in vitro differentiated dendritic cells and macrophages on the other hand. In addition, viability and apoptosis analyses were carried out successfully for Jurkat cell models. Studies on several species, including bacteria or fungi, demonstrate not only the capability to enumerate these cells, but also show that even other microbiological life cycle phases can be visualized. CONCLUSIONS: These results underline the potential of impedance spectroscopy flow cytometry as a valuable complement to other known cytometers and cell detection systems.

On-chip Non-reciprocal Optical Devices Based on Quantum Inspired Photonic Lattices

We propose integrated optical structures that can be used as isolators and polarization splitters based on engineered photonic lattices. Starting from optical waveguide arrays that mimic Fock space (quantum state with a well-defined particle number) representation of a non-interacting two-site Bose Hubbard Hamiltonian, we show that introducing magneto-optic nonreciprocity to these structures leads to a superior optical isolation performance. In the forward propagation direction, an input TM polarized beam experiences a perfect state transfer between the input and output waveguide channels while surface Bloch oscillations block the backward transmission between the same ports. Our analysis indicates a large isolation ratio of 75 dB after a propagation distance of 8mm inside seven coupled waveguides. Moreover, we demonstrate that, a judicious choice of the nonreciprocity in this same geometry can lead to perfect polarization splitting.

A STUDY ON THE FEASIBILITY OF UNIVERSAL CHIP CONTROL IN MACHINING

A novel solution to the long standing issue of chip entanglement and breakage in metal cutting is presented in this dissertation. Through this work, an attempt is made to achieve universal chip control in machining by using chip guidance and subsequent breakage by backward bending (tensile loading of the chip's rough top surface) to effectively control long continuous chips into small segments. One big limitation of using chip breaker geometries in disposable carbide inserts is that the application range is limited to a narrow band depending on cutting conditions. Even within a recommended operating range, chip breakers do not function effectively as designed due to the inherent variations of the cutting process. Moreover, for a particular process, matching the chip breaker geometry with the right cutting conditions to achieve effective chip control is a very iterative process. The existence of a large variety of proprietary chip breaker designs further exacerbates the problem of easily implementing a robust and comprehensive chip control technique. To address the need for a robust and universal chip control technique, a new method is proposed in this work. By using a single tool top form geometry coupled with a tooling system for inducing chip breaking by backward bending, the proposed method achieves comprehensive chip control over a wide range of cutting conditions. A geometry based model is developed to predict a variable edge inclination angle that guides the chip flow to a predetermined target location. Chip kinematics for the new tool geometry is examined via photographic evidence from experimental cutting trials. Both qualitative and quantitative methods are used to characterize the chip kinematics. Results from the chip characterization studies indicate that the chip flow and final form show a remarkable consistency across multiple levels of workpiece and tool configurations as well as cutting conditions. A new tooling system is then designed to comprehensively break the chip by backward bending. Test results with the new tooling system prove that by utilizing the chip guidance and backward bending mechanism, long continuous chips can be more consistently broken into smaller segments that are generally deemed acceptable or good chips. It is found that the proposed tool can be applied effectively over a wider range of cutting conditions than present chip breakers thus taking possibly the first step towards achieving universal chip control in machining.

IN-SITU TEM PLASMA CHIP NANOFABRICATION AND CHARACTERIZATION

A silicon-based microcell was fabricated with the potential for use in in-situ transmission electron microscopy (TEM) of materials under plasma processing. The microcell consisted of 50 nm-thick film of silicon nitride observation window with 60μm distance between two electrodes. E-beam scattering Mont Carlo simulation showed that the silicon nitride thin film would have very low scattering effect on TEM primary electron beam accelerated at 200 keV. Only 4.7% of primary electrons were scattered by silicon nitride thin film and the Ar gas (60 μm thick at 1 atm pressure) filling the space between silicon nitride films. Theoretical calculation also showed low absorption of high-energy e-beam electrons. Because the plasma cell needs to survive the high vacuum TEM chamber while holding 1 atm internal pressure, a finite element analysis was performed to find the maximum stress the low-stress silicon nitride thin film experienced under pressure. Considering the maximum burst stress of low-stress silicon nitride thin film, the simulation results showed that the 50 nm silicon nitride thin film can be used in TEM under 1 atm pressure as the observation window. Ex-situ plasma generation experiment demonstrated that air plasma can be ignited at DC voltage of 570. A Scanning electron microscopy (SEM) analysis showed that etching and deposition occurred during the plasma process and larger dendrites formed on the positive electrode.