On-Chip All-Optical Passive 3.55 Gbit/s NRZ-to-PRZ Format Conversion Using a High-Q Silicon-Based Microring Resonator

We report the experimental result of all-optical passive 3.55 Gbit/s non-return-to-zero (NRZ) to pseudo-return-to-zero (PRZ) format conversion using a high-quality-factor (Q-factor) silicon-based microring resonator notch filter on chip. The silicon-based microring resonator has 23800 Q-factor and 22 dB extinction ratio (ER), and the PRZ signals has about 108 ps width and 4.98 dB ER.

Fabrication of Silicon-Based Template-Assisted Nanoelectrode Arrays and Ohmic Contact Properties Investigation

A convenient fabrication technology for large-area, highly-ordered nanoelectrode arrays on silicon substrate has been described here, using porous anodic alumina (PAA) as a template. The ultrathin PAA membranes were anodic oxidized utilizing a two-step anodization method, from Al film evaporated on substrate. The purposes for the use of two-step anodization were, first, improving the regularity of the porous structures, and second reducing the thickness of the membranes to 100 similar to 200 nm we desired. Then the nanoelectrode arrays were obtained by electroless depositing Ni-W alloy into the through pores of PAA membranes, making the alloy isolated by the insulating pore walls and contacting with the silicon substrates at the bottoms of pores. The Ni-W alloy was also electroless deposited at the back surface of silicon to form back electrode. Then ohmic contact properties between silicon and Ni-W alloy were investigated after rapid thermal annealing. Scanning electron microscopy (SEM) observations showed the structure characteristics, and the influence factors of fabrication effect were discussed. The current voltage (I-V) curves revealed the contact properties. After annealing in N-2 at 700 degrees C, good linear property was shown with contact resistance of 33 Omega, which confirmed ohmic contacts between silicon and electrodes. These results presented significant application potential of this technology in nanosize current-injection devices in optoelectronics, microelectronics and bio-medical fields.

ELECTRON-STATES OF A STACKING-FAULT RIBBON IN SILICON

The electronic structure of a bounded intrinsic stacking fault in silicon is calculated. The method used is an LCAO-scheme (Linear Combinations of Atomic Orbitals) taking ten atomic orbitals of s-, p-, and d-type into account. The levels in the band gap are extracted using Lanczos' algorithm and a continued fraction representation of the local density of states. We find occupied states located up to 0.3 eV above the valence band maximum (E(v)). This significantly differs from the result obtained for the ideal infinite fault for which the interface state is located at E(v)+ 0.1 eV.

TEMPERATURE EFFECT ON POROUS SILICON LUMINESCENCE

A theoretical surface-state model of porous-silicon luminescence is proposed. The temperature effect on the PhotoLuminescence (PL) spectrum for pillar and spherical structures is considered, and it is found that the effect is dependent on the doping concentration, the excitation strength, and the shape and dimensions of the Si microstructure. The doping concentration has an effect on the PL intensity at high temperatures and the excitation strength has an effect on the PL intensity at low temperaturs. The variations of the PL intensity with temperature are different for the pillar and spherical structures. At low temperatures the PL intensity increases in the pillar structure, while in the spherical structure the PL intensity decreases as the temperature increases, at high temperatures the PL intensities have a maximum for both models. The temperature, at which the PL intensity reaches its maximum, depends on the doping concentration. The PL spectrum has a broader peak structure in the spherical structure than in the pillar structure. The theoretical results are in agreement with experimental results.