996 resultados para display technology


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Several of the newly developed drug molecules experience poor biopharmaceutical behavior, which hinders their effective delivery at the proper site of action. Among the several strategies employed in order to overcome this obstacle, mesoporous silicon-based materials have emerged as promising drug carriers due to their ability to improve the dissolution behavior of several poorly water-soluble drugs compounds confined within their pores. In addition to improve the dissolution behavior of the drugs, we report that porous silicon (PSi) nanoparticles have a higher degree of biocompatibility than PSi microparticles in several cell lines studied. In addition, the degradation of the nanoparticles showed its potential to fast clearance in the body. After oral delivery, the PSi particles were also found to transit the intestines without being absorbed. These results constituted the first quantitative analysis of the behavior of orally administered PSi nanoparticles compared with other delivery routes in rats. The self-assemble of a hydrophobin class II (HFBII) protein at the surface of hydrophobic PSi particles endowed the particles with greater biocompatibility in different cell lines, was found to reverse their hydrophobicity and also protected a drug loaded within its pores against premature release at low pH while enabling subsequent drug release as the pH increased. These results highlight the potential of HFBII-coating for PSi-based drug carriers in improving their hydrophilicity, biocompatibility and pH responsiveness in drug delivery applications. In conclusion, mesoporous silicon particles have been shown to be a versatile platform for improving the dissolution behavior of poorly water-soluble drugs with high biocompatibility and easy surface modification. The results of this study also provide information regarding the biofunctionalization of the THCPSi particles with a fungal protein, leading to an improvement in their biocompatibility and endowing them with pH responsive and mucoadhesive properties.

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Solar pond technology has made substantial progress in the last fifteen years. This paper reviews the basic principles of solar ponds and the problems encountered in their operation and maintenance. The factors which influence the technical and economic viability of solar ponds for thermal applications and power generation have been discussed.

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Design, fabrication and preliminary testing of a flat pump with millimetre thickness are described in this paper. The pump is entirely made of polymer materials barring the magnet and copper coils used for electromagnetic actuation. The fabrication is carried out using widely available microelectronic packaging machinery and techniques. Therefore, the fabrication of the pump is straightforward and inexpensive. Two types of prototypes are designed and built. One consists of copper coils that are etched on an epoxy plate and the other has wound insulated wire of 90 mu m diameter to serve as a coil. The overall size of the first pump is 25 mm x 25 mm x 3.6 mm including the 3.1 mm-thick NdFeB magnet of diameter 12 mm. It consists of a pump chamber of 20 mm x 20 mm x 0.8 mm with copper coils etched from a copper-clad epoxy plate using dry-film lithography and milled using a CNC milling machine, two passive valves and the pump-diaphragm made of Kapton film of 0.089 mm thickness. The second pump has an overall size of 35 mm x 35 mm x 4.4 mm including the magnet and the windings. A breadboard circuit and DC power supply are used to test the pump by applying an alternating square-wave voltage pulse. A water slug in a tube attached to the inlet is used to observe and measure the air-flow induced by the pump against atmospheric pressure. The maximum flow rate was found to be 15 ml/min for a voltage of 2.5 V and a current of 19 mA at 68 Hz.

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A graphical display of the frequency content of background,electroencephalogram (EEG) activity is obtained by calculating the spectral estimates using autocorrelation autoregressive method and the classical Fourier transform method, Display of spectral content of consecutive data segments is made using hidden-line suppression technique so as to get a spectral array, The autoregressive spectral array (ASA) is found to be sensitive to baseline drift, Following baseline correction the autoregressive technique is found to be superior to the Fourier method of compressed spectral array (CSA) in detecting the transitions in the frequencies of the signal. The smoothed ASA gives a better picture of transitions and changes in the background activity, The ASA can be made to adapt to specific changes of dominant frequencies while eliminating unnecessary peaks in the spectrum. The utility,of the ASA for background EEG analysis is discussed,

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The emergence of optoelectronics and photonics as viable alternatives to electronics in many key areas of engineering relevance is indeed significant. This paper presents a tutorial review of integrated optics � a technologically important development in photonics. Materials, processes, device technology and applications are highlighted.

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Wave pipelining is a design technique for increasing the throughput of a digital circuit or system without introducing pipelining registers between adjacent combinational logic blocks in the circuit/system. However, this requires balancing of the delays along all the paths from the input to the output which comes the way of its implementation. Static CMOS is inherently susceptible to delay variation with input data, and hence, receives a low priority for wave pipelined digital design. On the other hand, ECL and CML, which are amenable to wave pipelining, lack the compactness and low power attributes of CMOS. In this paper we attempt to exploit wave pipelining in CMOS technology. We use a single generic building block in Normal Process Complementary Pass Transistor Logic (NPCPL), modeled after CPL, to achieve equal delay along all the propagation paths in the logic structure. An 8×8 b multiplier is designed using this logic in a 0.8 ?m technology. The carry-save multiplier architecture is modified suitably to support wave pipelining, viz., the logic depth of all the paths are made identical. The 1 mm×0.6 mm multiplier core supports a throughput of 400 MHz and dissipates a total power of 0.6 W. We develop simple enhancements to the NPCPL building blocks that allow the multiplier to sustain throughputs in excess of 600 MHz. The methodology can be extended to introduce wave pipelining in other circuits as well

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Recent advances in nonsilica fiber technology have prompted the development of suitable materials for devices operating beyond 1.55 mu m. The III-V ternaries and quaternaries (AlGaIn)(AsSb) lattice matched to GaSb seem to be the obvious choice and have turned out to be promising candidates for high speed electronic and long wavelength photonic devices. Consequently, there has been tremendous upthrust in research activities of GaSb-based systems. As a matter of fact, this compound has proved to be an interesting material for both basic and applied research. At present, GaSb technology is in its infancy and considerable research has to be carried out before it can be employed for large scale device fabrication. This article presents an up to date comprehensive account of research carried out hitherto. It explores in detail the material aspects of GaSb starting from crystal growth in bulk and epitaxial form, post growth material processing to device feasibility. An overview of the lattice, electronic, transport, optical and device related properties is presented. Some of the current areas of research and development have been critically reviewed and their significance for both understanding the basic physics as well as for device applications are addressed. These include the role of defects and impurities on the structural, optical and electrical properties of the material, various techniques employed for surface and bulk defect passivation and their effect on the device characteristics, development of novel device structures, etc. Several avenues where further work is required in order to upgrade this III-V compound for optoelectronic devices are listed. It is concluded that the present day knowledge in this material system is sufficient to understand the basic properties and what should be more vigorously pursued is their implementation for device fabrication. (C) 1997 American Institute of Physics.

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The aim of logic synthesis is to produce circuits which satisfy the given boolean function while meeting timing constraints and requiring the minimum silicon area. Logic synthesis involves two steps namely logic decomposition and technology mapping. Existing methods treat the two as separate operation. The traditional approach is to minimize the number of literals without considering the target technology during the decomposition phase. The decomposed expressions are then mapped on to the target technology to optimize the area, Timing optimization is carried out subsequently, A new approach which treats logic decomposition and technology maping as a single operation is presented. The logic decomposition is based on the parameters of the target technology. The area and timing optimization is carried out during logic decomposition phase itself. Results using MCNC circuits are presented to show that this method produces circuits which are 38% faster while requiring 14% increase in area.

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This article explores issues and challenges in the field of education in nanoscience and technology with special emphasis with respect to India, where an expanding programme of research in nano science and technology is in place. The article does not concentrate on actual curricula that are needed in nano science and technology education course. Rather it focuses on the desirability of nanoscience and technology education at different levels of education and future prospect of students venturing into this within the economic and cultural milieu of India. We argue that care is needed in developing the education programme in India. However, the risk is worth taking as the education on nanoscience and technology can bridge the man power gap not only in this area of technology but also related technologies of hardware and micro electronics for which the country is a promising destination at global level. This will also unlock the demographical advantage that India will enjoy in the next five decades.

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This paper analyses the influence of management on Technical Efficiency Change (TEC) and Technological Progress (TP) in the communication equipment and consumer electronics sub-sectors of Indian hardware electronics industry. Each sub-sector comprises 13 sample firms for two time periods.The primary objective is to determine the relative contribution of TP and TEC to TFP Growth (TFPG) and to establish the influence of firm specific operational management decision variables on these two components. The study finds that both the sub-sectors have strived and achieved steady TP but not TEC in the period of economic liberalisation to cope with the intensifying competition. The management decisions with respect to asset and profit utilization, vertical integration, among others, improved TP and TE in the sub-sectors. However, R&D investments and technology imports proved costly for TFP indicating inadequate efforts and/or poor resource utilisation by the management. Management was found to be complacent in terms of improving or developing their own technology as indicated by their higher dependence on import of raw materials and no influence of R&D on TP.