Characterization and improvement of GaAs layers grown on Si using an ultrathin a-Si film as a buffer layer

GaAs epilayers grown on Si by metalorganic chemical vapor deposition (MOCVD) using an ultrathin a-Si buffer layer were characterized by deep-level transient spectroscopy (DLTS). Six electron traps with activation energies of 0.79, 0.67, 0.61, 0.55, 0.53 and 0.32 eV below the conduction band were determined by fitting the experimental spectra. Two of the levels, C (0.61 eV) and F (0.32 eV), were first detected in GaAs epilayers on Si and identified as the metastable defects M3 and M4, respectively. In order to improve the quality of GaAs/Si epilayers, another GaAs layer was grown on the GaAs/Si epilayers grown using MOCVD. The deep levels in this regrown GaAs epilayer were also studied using DLTS. Only the EL2 level was found in the regrown GaAs epilayers. These results show that the quality of the GaAs epilayer was greatly improved by applying this growth process.

An Improvement on 2× 2 Silicon-on-Insulator Mach-Zehnder Thermo-Optical Switch

An improved 2 ×2 silicon-on-insulator Mach-Zehnder thermo-optical switch is designed and fabricated, which is based on strongly guided multimode interference couplers and single- mode phase-shifting arms. The multimode interference couplers and input/output waveguides are deeply etched to improve coupler performances and coupler-waveguide coupling efficiencies. However, shallow etching is used in the phase-shifting arms to guarantee single-mode property. The strongly guided coupler presents an attractive uniformity about 0. 03 dB and a low propagation loss of -0.6 dB. The 2× 2 switch shows an insertion loss as low as -6.8 dB, where the fiber-waveguide coupling loss of -4.3 dB is included, and the response-time is measured as short as 6.8 μs, which are much better than our previous results.

Improvement of CMOS SOS devices characteristics by a modified solid phase epitaxy

CMOS/SOS devices have lower carriers mobility and higher channel leakage current than bulk silicon CMOS devices. These mainly results from the defects of heteroepitaxial silicon film, especially from the defects near Si-Sapphire interface. This paper describes the experiment results of CMOS/SOS devices characteristics improved by a better epitaxial silicon quality which is obtained by a modified solid phase epitaxy.

Quality improvement of GaInNAs/GaAs quantum wells grown by plasma-assisted molecular beam epitaxy

The optimum growth condition of GaInNAs/GaAs quantum wells (QWs) by plasma-assisted molecular beam epitaxy was investigated. High-resolution X-ray diffraction and photoluminescence (PL) measurements showed that ion damage drastically degraded the quality of GaNAs and GaInNAs QWs and that ion removal magnets can effectively remove the excess ion damage. Remarkable improvement of PL intensity and obvious appearance of pendellosung fringes were observed by removing the N ions produced in the plasma cell. When the growth rate increased from 0.73 to 1.2 ML/s, the optimum growth temperature was raised from 460 degreesC to 480 degreesC and PL peak intensity increased two times. Although the N composition decreased with increasing growth rate, degradation of optical properties of GaInNAs QWs was observed when the growth rate was over 0.92 ML/s. Due to low-temperature growth of GaInNAs QWs, a distinctive reflection high-energy electron diffraction pattern was observed only when the GaAs barrier was grown under lower As-4 pressure. The samples with GaAs barriers grown under lower As-4 pressure (V/III ratio about 24) exhibited seven times increase in PL peak intensity compared with those grown under higher As-4 pressure (V/III ratio about 50). (C) 2001 Elsevier Science B,V. All rights reserved.

Improvement of thin silicon on sapphire (SOS) film materials and device performances by solid phase epitaxy

The increased emphasis on sub-micron CMOS/SOS devices has placed a demand for high quality thin silicon on sapphire (SOS) films with thickness of the order 100-200 nm. It is demonstrated that the crystalline quality of as-grown thin SOS films by the CVD method can be greatly improved by solid phase epitaxy (SPE) process: implantation of self-silicon ions and subsequent thermal annealing. Subsequent regrowth of this amorphous layer leads to a greater improvement in silicon layer crystallinity and channel carrier mobility, evidenced, respectively, by double crystal X-ray diffraction and electrical measurements. We concluded that the thin SPE SOS films are suitable for application to high-performance CMOS circuitry. (C) 2000 Elsevier Science S.A. All rights reserved.

Stability improvement of selective oxidation during the fabrication of InGaAs/GaAs vertical cavity surface emitting laser

The effects of the carrier gas flow and water temperature on the oxidation rate for different reaction temperatures were investigated. The optimum conditions for stable oxidation were obtained. Two mechanisms of the oxidation process are revealed. One is the flow-controlling process, which is unstable. The other is the temperature-controlling process, which is stable. The stable region decreases for higher reaction temperatures. The simulation results for the stable oxidation region are also given. With optimum oxidation conditions, the stability and precision of the oxidation can be dramatically improved.