2.4 GHz Class-E power amplifier with transmissionline harmonic terminations

The design procedure, fabrication and measurement of a Class-E power amplifier with excellent second- and third-harmonic suppression levels are presented. A simplified design technique offering compact physical layout is proposed. With a 1.2 mm gate-width GaAs MESFET as a switching device, the amplifier is capable of delivering 19.2 dBm output power at 2.41 GHz, achieves peak PAE of 60% and drain efficiency of 69%, and exhibits 9 dB power gain when operated from a 3 V DC supply voltage. When compared to the classical Class-E two-harmonic termination amplifier, the Class-E amplifier employing three-harmonic terminations has more than 10% higher drain efficiency and 23 dB better third-harmonic suppression level. Experimental results are presented and good agreement with simulation is obtained. Further, to verify the practical implementation in communication systems, the Bluetooth-standard GFSK modulated signal is applied to both two- and three-harmonic amplifiers. The measured RMS FSK deviation error and RMS magnitude error were, for the three-harmonic case, 1.01 kHz and 0.122%, respectively, and, for the two-harmonic case, 1.09 kHz and 0.133%. © 2007 The Institution of Engineering and Technology.

Improving f(MAX)/f(T) ratio in FinFETs using source/drain extension region engineering

A design methodology to optimise the ratio of maximum oscillation frequency to cutoff frequency, f(MAX)/f(T), in 60 nm FinFETs is presented. Results show that 25 to 60% improvement in f(MAX)/f(T) at drain currents of 20-300 mu A/mu m can be achieved in a non-overlap gate-source/drain architecture. The reported work provides new insights into the design and optimisation of nanoscale FinFETs for RF applications.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

Accurate substrate modelling of RF CMOS

The losses within the substrate of an RF IC can have significant effect on performance in a mixed signal application. in order to model substrate coupling accurately, it is represented by an RC network to account for both resistive and dielectric losses at high frequency (> 1 GHz). A small-signal equivalent circuit model of an RF IC inclusive of substrate parasitic effect is analysed in terms of its y-parameters and an extraction procedure for substrate parameters has been developed. By coupling the extracted substrate parameters along with extrinsic resistances associated with gate, source and drain, a standard BSIM3 model has been extended for RF applications. The new model exhibits a significant improvement in prediction of output reflection coefficient S-22 in the frequency range from 1 to 10 GHz in device mode of operation and for a low noise amplifier (LNA) at 2.4 GHz. Copyright (C) 2006 John Wiley & Sons, Ltd.

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers

A comparison of dc characteristics of fully depleted double-gate (DG) MOSFETs with respect to low-power circuit applications and device scaling has been performed by two-dimensional device simulation. Three different DG MOSFET structures including a conventional N+ polysilicon gate device with highly doped Si layer, an asymmetrical P+/N+ polysilicon gate device with low doped Si layer and a midgap metal gate device with low doped Si layer have been analysed. It was found that DG MOSFET with mid-gap metal, gates yields the best dc parameters for given off-state drain leakage current and highest immunity to the variation of technology parameters (gate length, gate oxide thickness and Si layer thickness). It is also found that an asymmetrical P+/N+ polysilicon gate DG MOSFET design offers comparable dc characteristics, but better parameter immunity to technology tolerances than a conventional DG MOSFET. (C) 2004 Elsevier Ltd. All rights reserved.

Fathers’ Views and Understanding of their Roles in Families with a Child with Acute Lymphoblastic Leukaemia: An Interpretative Phenomenological Analysis

This study explored how fathers of children diagnosed with acute lymphoblastic leukaemia (ALL) perceived and understood the roles they had within their family over the course of their child’s illness and treatment. In-depth semi-structured interviews were conducted with five fathers. Transcripts were analysed using interpretative phenomenological analysis (IPA). The major themes that emerged were: adjusting to the diagnosis; the experience of maternal gate-keeping; striving for normalization; experiences of giving and receiving support. Overall, the fathers perceived themselves as having significant responsibility in helping their child and family cope with the illness experience. Clinical implications, including the need for professionals to recognize and more openly acknowledge the father’s position, are considered.

Solid-bound, proton-driven, fluorescent ‘off–on–off’ switches based on PET (photoinduced electron transfer)

Anthracene-based, H+-driven, ‘off–on–off’ fluorescent PET (photoinduced electron transfer) switches are immobilized on organic and inorganic polymeric solids in the form of Tentagel® and silica, respectively. The environment of the organic bead displaces apparent switching thresholds towards lower pH values whereas the Si–O- groups of silica electrostatically cause the opposite effect. These switches are ternary logic gate tags, one of which can be particularly useful in strengthening molecular computational identification (MCID) of small solid objects.

Decoherence-based exploration of d-dimensional one-way quantum computation: Information transfer and basic gates

We study the effects of amplitude and phase damping decoherence in d-dimensional one-way quantum computation. We focus our attention on low dimensions and elementary unidimensional cluster state resources. Our investigation shows how information transfer and entangling gate simulations are affected for d >= 2. To understand motivations for extending the one-way model to higher dimensions, we describe how basic qudit cluster states deteriorate under environmental noise of experimental interest. In order to protect quantum information from the environment, we consider encoding logical qubits into qudits and compare entangled pairs of linear qubit-cluster states to single qudit clusters of equal length and total dimension. A significant reduction in the performance of cluster state resources for d > 2 is found when Markovian-type decoherence models are present.

From stress to distress: Conceptualizing the British family farming patriarchal way of life

‘Rural stress’ and ‘farming stress’ are terms that have become commonly appropriated by British health-based academic disciplines, the medical profession and social support networks, especially since the agricultural ‘crises’ of B.S.E. and Foot and Mouth Disease. Looking beyond the media headlines, it is apparent that the terms in fact are colloquial catch-alls for visible psychological and physiological outcomes shown by individuals. Seldom have the underlying causes and origins of presentable medical outcomes been probed, particularly within the context of the patriarchal and traditionally patrilineal way of life which family forms of farming business activity in Britain encapsulate. Thus, this paper argues that insufficient attention has been paid to the conceptualization of the terms. They have become both over-used and ill-defined in their application to British family farm individuals and their life situations. A conceptual framework is outlined that attempts to shift the stress research agenda into the unilluminated spaces of the family farming ‘way of life’ and focus instead on ‘distress’. Drawing upon theorization from agricultural and feminist geography together with cultural approaches from rural geography, four distinct clusters of distress originate from the thoughts of individuals and the social practices now required to enact patriarchal family farming gender identities. These are explored using case study evidence from ethnographic repeated life history interviews with members of seven farming families in Powys, Mid Wales, an area dominated by family forms of farming business. Future research agendas need to be based firmly on the distressing reality of patriarchal family farming and also be inclusive of those who, having rejected the associated way of life, now lie beyond the farm gate.

From PASS 1 to YES to AND logic: building parallel processing into molecular logic gates by sequential addition of receptors

The synthesis and photophysical characterization of a novel molecular logic gate 4, operating in water, is demonstrated based on the competition between. fluorescence and photoinduced electron transfer (PET). It is constructed according to a 'fluorophore-spacer-receptor(1)-spacer-receptor(2)' format where anthracene is the. fluorophore, receptor(1) is a tertiary amine and receptor(2) is a phenyliminodiacetate ligand. Using only protons and zinc cations as the chemical inputs and. fluorescence as the output, 4 is demonstrated to be both a two-input AND and INH logic gate. When 4 is examined in context to the YES logic gates 1 and 2, and the two-input AND logic gate 3 and three-input AND logic gate 5, each with one or more of the following receptors including a tertiary amine, phenyliminodiacetate or benzo-15-crown-5 ether, logic gate 4 is the missing link in the homologous series. Collectively, the molecular logic gates 1-5 corroborate the PET 'fluorophore-spacer-receptor' model using chemical inputs and a light-signal output and provide insight into controlling the. fluorescence quantum yield of future PET-based molecular logic gates.

Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding

A new domain-specific, reconfigurable system-on-a-chip (SoC) architecture is proposed for video motion estimation. This has been designed to cover most of the common block-based video coding standards, including MPEG-2, MPEG-4, H.264, WMV-9 and AVS. The architecture exhibits simple control, high throughput and relatively low hardware cost when compared with existing circuits. It can also easily handle flexible search ranges without any increase in silicon area and can be configured prior to the start of the motion estimation process for a specific standard. The computational rates achieved make the circuit suitable for high-end video processing applications, such as HDTV. Silicon design studies indicate that circuits based on this approach incur only a relatively small penalty in terms of power dissipation and silicon area when compared with implementations for specific standards. Indeed, the cost/performance achieved exceeds that of existing but specific solutions and greatly exceeds that of general purpose field programmable gate array (FPGA) designs.

Electrical characterization of ALD Al2O3 and HfO2 films on germanium

Al2O3 and HfO2 films were deposited on germanium substrates by atomic layer deposition (ALD) and analyzed by MOS capacitor electrical characterization. In-situ plasma nitridation performed prior to ALD was found to improve the stability of the interface. For Al 2O3/GeON/Ge capacitors, a 450°C anneal in nitrogen ambient reduced hysteresis and oxide fixed charge to 90 mV and 1012 cm-2 respectively, with low leakage current density. On the contrary, degradation was observed for un-nitrided Al2O3/Ge capacitors after 300 and 400°C post-metal anneals. HfO2/GeON/Ge capacitors benefitted from a 400°C densification anneal but exhibited degradation after post-metal anneals at temperatures greater than 300°C. This degradation is attributed to the influence of Al electrodes on the HfO 2 gate stack. HfO2 is considered to be a suitable material for the gate stack and Al2O3 for the buried dielectric in a GeOI structure. ©The Electrochemical Society.