Low-thermal-budget solution processing of thin films of zinc ferrite and other complex oxides

Further miniaturization of magnetic and electronic devices demands thin films of advanced nanomaterials with unique properties. Spinel ferrites have been studied extensively owing to their interesting magnetic and electrical properties coupled with stability against oxidation. Being an important ferrospinel, zinc ferrite has wide applications in the biological (MRI) and electronics (RF-CMOS) arenas. The performance of an oxide like ZnFe2O4 depends on stoichiometry (defect structure), and technological applications require thin films of high density, low porosity and controlled microstructure, which depend on the preparation process. While there are many methods for the synthesis of polycrystalline ZnFe2O4 powder, few methods exist for the deposition of its thin films, where prolonged processing at elevated temperature is not required. We report a novel, microwave-assisted, low temperature (<100°C) deposition process that is conducted in the liquid medium, developed for obtaining high quality, polycrystalline ZnFe2O4 thin films on technologically important substrates like Si(100). An environment-friendly solvent (ethanol) and non-hazardous oxide precursors (β-diketonates of Zn and Fe in 1:2 molar ratio), forming a solution together, is subjected to irradiation in a domestic microwave oven (2.45 GHz) for a few minutes, leading to reactions which result in the deposition of ZnFe2O4 films on Si (100) substrates suspended in the solution. Selected surfactants added to the reactant solution in optimum concentration can be used to control film microstructure. The nominal temperature of the irradiated solution, i.e., film deposition temperature, seldom exceeds 100°C, thus sharply lowering the thermal budget. Surface roughness and uniformity of large area depositions (50x50 mm2) are controlled by tweaking the concentration of the mother solution. Thickness of the films thus grown on Si (100) within 5 min of microwave irradiation can be as high as several microns. The present process, not requiring a vacuum system, carries a very low thermal budget and, together with a proper choice of solvents, is compatible with CMOS integration. This novel solution-based process for depositing highly resistive, adherent, smooth ferrimagnetic films on Si (100) is promising to RF engineers for the fabrication of passive circuit components. It is readily extended to a wide variety of functional oxide films.

Power scalable digital baseband architecture for IEEE 802.15.4

We propose a power scalable digital base band for a low-IF receiver for IEEE 802.15.4-2006. The digital section's sampling frequency and bit width are used as knobs to reduce the power under favorable signal and interference scenarios, thus recovering the design margins introduced to handle worst case conditions. We propose tuning of these knobs based on measurements of Signal and the interference levels. We show that in a 0.13u CMOS technology, for an adaptive digital base band section of the receiver designed to meet the 802.15.4 standard specification, power saving can be up to nearly 85% (0.49mW against 3.3mW) in favorable interference and signal conditions.

A tuned rectifier for RF energy harvesting from ambient radiations

A circuit topology based on accumulate-and-use philosophy has been developed to harvest RF energy from ambient radiations such as those from cellular towers. Main functional units of this system are antenna, tuned rectifier, supercapacitor, a gated boost converter and the necessary power management circuits. Various RF aspects of the design philosophy for maximizing the conversion efficiency at an input power level of 15 mu W are presented here. The system is characterized in an anechoic chamber and it has been established that this topology can harvest RF power densities as low as 180 mu W/m(2) and can adaptively operate the load depending on the incident radiation levels. The output of this system can be easily configured at a desired voltage in the range 2.2-4.5 V. A practical CMOS load - a low power wireless radio module has been demonstrated to operate intermittently by this approach. This topology can be easily modified for driving other practical loads, from harvested RF energy at different frequencies and power levels.

Visualization of coherent structures in turbulent subsonic jet using planar laser induced fluorescence of acetone

In this paper, we present the molecular density distribution measurement in turbulent nitrogen jet (Re approximate to 3 x 10(3)), using acetone as molecular tracer. The tracer was seeded in the nitrogen jet by purging through the liquid acetone at ambient temperature. Planar laser sheet of 266 nm wavelength from frequency quadrupled, Q-switched, Nd:YAG laser was used as an excitation source. Emitted fluorescence images of jet flow field were recorded on CMOS camera. The dependence of planar laser induced fluorescence (PLIF) intensity on acetone vapor density was used to convert PLIF image of nitrogen jet into the density image on pixel-by-pixel basis. Instantaneous quantitative density image of nitrogen jet, seeded with acetone, was obtained. The arrowhead-shaped coherent turbulent structures were observed in the present work. It was found that coherent structures were non-overlapping with separate boundaries. Breaking of coherent structures into turbulence was clearly observed above four times jet width.

An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording

Low power consumption per channel and data rate minimization are two key challenges which need to be addressed in future generations of neural recording systems (NRS). Power consumption can be reduced by avoiding unnecessary processing whereas data rate is greatly decreased by sending spike time-stamps along with spike features as opposed to raw digitized data. Dynamic range in NRS can vary with time due to change in electrode-neuron distance or background noise, which demands adaptability. An analog-to-digital converter (ADC) is one of the most important blocks in a NRS. This paper presents an 8-bit SAR ADC in 0.13-mu m CMOS technology along with input and reference buffer. A novel energy efficient digital-to-analog converter switching scheme is proposed, which consumes 37% less energy than the present state-of-the-art. The use of a ping-pong input sampling scheme is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the data rate, the A/D process is only enabled through the in-built background noise rejection logic to ensure that the noise is not processed. The ADC resolution can be adjusted from 8 to 1 bit in 1-bit step based on the input dynamic range. The ADC consumes 8.8 mu W from 1 V supply at 1 MS/s speed. It achieves effective number of bits of 7.7 bits and FoM of 42.3 fJ/conversion-step.

Asynchronous Measurement of Transient Phase-Shift Resulting From RF Receiver State-Change

In a wireless receiver, a down-converted RF signal undergoes a transient phase shift, when the gain state is changed to adjust for varying conditions in transmission and propagation. A method is developed, in which such phase shifts are detected asynchronously, and their undesirable effects on the bit error rate are corrected. The method was developed for and used in, the system-level characterization and calibration of a 65-nm CMOS UHF receiver. The phase-shifts associated with specific gain-state transitions were measured within a test framework, and used in the baseband signal processing blocks to compensate for errors, whenever the receiver anticipated a gain-state transition.

Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13-mu m CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.

Time-Based All-Digital Technique for Analog Built-in Self-Test

A scheme for built-in self-test of analog signals with minimal area overhead for measuring on-chip voltages in an all-digital manner is presented. The method is well suited for a distributed architecture, where the routing of analog signals over long paths is minimized. A clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head present at each test node, which consists of a pair of delay cells and a pair of flip-flops, locally converts the test voltage to a skew between a pair of subsampled signals, thus giving rise to as many subsampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding subsampled signal pair is fed to a delay measurement unit to measure the skew between this pair. The concept is validated by designing a test chip in a UMC 130-nm CMOS process. Sub-millivolt accuracy for static signals is demonstrated for a measurement time of a few seconds, and an effective number of bits of 5.29 is demonstrated for low-bandwidth signals in the absence of sample-and-hold circuitry.