A double data rate (DDR) architecture for OFDM based wireless consumer devices

The creation of OFDM based Wireless Personal Area Networks (WPANs) has allowed the development of high bit-rate wireless communication devices suitable for streaming High Definition video between consumer products, as demonstrated in Wireless-USB and Wireless-HDMI. However, these devices need high frequency clock rates, particularly for the OFDM, FFT and symbol processing sections resulting in high silicon cost and high electrical power. The high clock rates make hardware prototyping difficult and verification is therefore very important but costly. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a Double Data Rate (DDR) architecture for implementation inside a OFDM baseband codec in order to reduce the high frequency clock rates by a complete factor of 2. The presented architecture has been implemented and tested for ECMA-368 (Wireless- USB context) resulting in a maximum clock rate of 264MHz instead of the expected 528MHz clock rate existing anywhere on the baseband codec die.

A double data rate (DDR) architecture for OFDM based wireless consumer devices

The creation of OFDM based Wireless Personal Area Networks (WPANs) has allowed high bit-rate wireless communication devices suitable for streaming High Definition video between consumer products as demonstrated in Wireless- USB. However, these devices need high clock rates, particularly for the OFDM sections resulting in high silicon cost and high electrical power. Acknowledging that electrical power in wireless consumer devices is more critical than the number of implemented logic gates, this paper presents a Double Data Rate (DDR) architecture to reduce the OFDM input and output clock rate by a factor of 2. The architecture has been implemented and tested for Wireless-USB (ECMA-368) resulting in a maximum clock of 264MHz instead of 528MHz existing anywhere on the die.

4,4 '-Dipyridyl-N,N '-dioxide complexes of metal-thiocyanate/selenocyanate: pi-stacked molecular rods as three-dimensional support for two-dimensional polymeric sheets and intra/interchain S center dot center dot center dot S interaction dependent architecture of the R-2(2)(8) synthon driven assembly of one-dimensional polymeric chains

Three supramolecular complexes of Co(II) using SCN-/SeCN- in combination with 4,4'-dipyridyl-N,N'-dioxide (dpyo), i.e., {[Co(SCN)(2)(dpyo)(2)].(dpyo)}(n) ( 1), {[Co(SCN)(2)(dpyo)(H2O)(2)].(H2O)}(n) ( 2), {[Co(SeCN)(2)(dpyo)(H2O)(2)]center dot(H2O)}(n) ( 3), have been synthesized and characterized by single-crystal X-ray analysis. Complex 1 is a rare example of a dpyo bridged two-dimensional (2D) coordination polymer, and pi-stacked dpyo supramolecular rods are generated by the lattice dpyo, passing through the rhombic grid of stacked layers, resulting in a three-dimensional (3D) superstructure. Complexes 2 and 3 are isomorphous one-dimensional (1D) coordination polymers [-Co-dpyo-Co-] that undergo self-assembly leading to a bilayer architecture derived through an R-2(2)(8) H-bonding synthon between coordinated water and dpyo oxygen. A reinvestigation of coordination polymers [Mn(SCN)(2)(dpyo)( H2O)(MeOH)](n) ( 4) and {[Fe(SCN)(2)(dpyo)(H2O)(2)]center dot(H2O)}(n) ( 5) reported recently by our group [ Manna et al. Indian J. Chem. 2006, 45A, 1813] reveals brick wall topology rather than bilayer architecture is due to the decisive role of S center dot center dot center dot S/Se center dot center dot center dot Se interactions in determining the helical nature in 4 and 5 as compared to zigzag polymeric chains in 2 and 3, although the same R-2(2)(8) synthon is responsible for supramolecular assembly in these complexes.

The Crucial Role of Polyatomic Anions in Molecular Architecture: Structural And Magnetic Versatility of Five Nickel(II) Complexes Derived from A N,N,O-Donor Schiff Base Ligand

A series of five Ni(II)-complexes containing the same tridentate Schiff base but different monoanionic ligands (N-3(-), NO3-, PhCOO- and NO2-)reveals that the competitive as well as the cooperative role of the monoanions and phenoxo group in bridging the metal ions play the key role in the variation of molecular architecture.

The internet, information architecture and community memory

This article reviews current technological developments, particularly Peer-to-Peer technologies and Distributed Data Systems, and their value to community memory projects, particularly those concerned with the preservation of the cultural, literary and administrative data of cultures which have suffered genocide or are at risk of genocide. It draws attention to the comparatively good representation online of genocide denial groups and changes in the technological strategies of holocaust denial and other far-right groups. It draws on the author's work in providing IT support for a UK-based Non-Governmental Organization providing support for survivors of genocide in Rwanda.

Workflow data exchange semantics, object discovery & integration architecture for cross media production & distribution

There has been a clear lack of common data exchange semantics for inter-organisational workflow management systems where the research has mainly focused on technical issues rather than language constructs. This paper presents the neutral data exchanges semantics required for the workflow integration within the AXAEDIS framework and presents the mechanism for object discovery from the object repository where little or no knowledge about the object is available. The paper also presents workflow independent integration architecture with the AXAEDIS Framework.

Hierarchical composite regular parallel architecture

The design space of emerging heterogenous multi-core architectures with re-configurability element makes it feasible to design mixed fine-grained and coarse-grained parallel architectures. This paper presents a hierarchical composite array design which extends the curret design space of regular array design by combining a sequence of transformations. This technique is applied to derive a new design of a pipelined parallel regular array with different dataflow between phases of computation.