993 resultados para Voltage stabilizing circuits
Resumo:
In multi-terminal high voltage direct current (HVDC) grids, the widely deployed droop control strategies will cause a non-uniform voltage deviation on the power flow, which is determined by the network topology and droop settings. This voltage deviation results in an inconsistent power flow pattern when the dispatch references are changed, which could be detrimental to the operation and seamless integration of HVDC grids. In this paper, a novel droop setting design method is proposed to address this problem for a more precise power dispatch. The effects of voltage deviations on the power sharing accuracy and transmission loss are analysed. This paper shows that there is a trade-off between minimizing the voltage deviation, ensuring a proper power delivery and reducing the total transmission loss in the droop setting design. The efficacy of the proposed method is confirmed by simulation studies.
Adaptive backstepping droop controller design for multi-terminal high-voltage direct current systems
Resumo:
Wind power is one of the most developed renewable energy resources worldwide. To integrate offshore wind farms to onshore grids, the high-voltage direct current (HVDC) transmission cables interfaced with voltage source converters (VSCs) are considered to be a better solution than conventional approaches. Proper DC voltage indicates successive power transfer. To connect more than one onshore grid, the DC voltage droop control is one of the most popular methods to share the control burden between different terminals. However, the challenges are that small droop gains will cause voltage deviations, while higher droop gain settings will cause large oscillations. This study aims to enhance the performance of the traditional droop controller by considering the DC cable dynamics. Based on the backstepping control concept, DC cables are modelled with a series of capacitors and inductors. The final droop control law is deduced step-by-step from the original remote side. At each step the control error from the previous step is considered. Simulation results show that both the voltage deviations and oscillations can be effectively reduced using the proposed method. Further, power sharing between different terminals can be effectively simplified such that it correlates linearly with the droop gains, thus enabling simple yet accurate system operation and control.
Resumo:
A new approach to determine the local boundary of voltage stability region in a cut-set power space (CVSR) is presented. Power flow tracing is first used to determine the generator-load pair most sensitive to each branch in the interface. The generator-load pairs are then used to realize accurate small disturbances by controlling the branch power flow in increasing and decreasing directions to obtain new equilibrium points around the initial equilibrium point. And, continuous power flow is used starting from such new points to get the corresponding critical points around the initial critical point on the CVSR boundary. Then a hyperplane cross the initial critical point can be calculated by solving a set of linear algebraic equations. Finally, the presented method is validated by some systems, including New England 39-bus system, IEEE 118-bus system, and EPRI-1000 bus system. It can be revealed that the method is computationally more efficient and has less approximation error. It provides a useful approach for power system online voltage stability monitoring and assessment. This work is supported by National Natural Science Foundation of China (No. 50707019), Special Fund of the National Basic Research Program of China (No. 2009CB219701), Foundation for the Author of National Excellent Doctoral Dissertation of PR China (No. 200439), Tianjin Municipal Science and Technology Development Program (No. 09JCZDJC25000), National Major Project of Scientific and Technical Supporting Programs of China During the 11th Five-year Plan Period (No. 2006BAJ03A06). ©2009 State Grid Electric Power Research Institute Press.
Resumo:
Power electronics plays an important role in the control and conversion of modern electric power systems. In particular, to integrate various renewable energies using DC transmissions and to provide more flexible power control in AC systems, significant efforts have been made in the modulation and control of power electronics devices. Pulse width modulation (PWM) is a well developed technology in the conversion between AC and DC power sources, especially for the purpose of harmonics reduction and energy optimization. As a fundamental decoupled control method, vector control with PI controllers has been widely used in power systems. However, significant power loss occurs during the operation of these devices, and the loss is often dissipated in the form of heat, leading to significant maintenance effort. Though much work has been done to improve the power electronics design, little has focused so far on the investigation of the controller design to reduce the controller energy consumption (leading to power loss in power electronics) while maintaining acceptable system performance. This paper aims to bridge the gap and investigates their correlations. It is shown a more thoughtful controller design can achieve better balance between energy consumption in power electronics control and system performance, which potentially leads to significant energy saving for integration of renewable power sources.
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The principle aspects of passive intermodulation (PIM) characterisation in distributed printed circuits with cascaded lumped nonlinearities are presented. Mechanisms of PIM generations have been investigated experimentally and modelled using the formalism of X-parameters. The devised equivalent circuit models are applied to the analysis of microstrip lines with distributed and cascaded lumped sources of nonlinearity. The dynamic measurements have revealed that PIM generation rates in straight and meandered microstrip lines differ and significantly deviate from those expected for the respective discrete sources of nonlinearity. The obtained results indicate that multiple physical sources of nonlinearity contribute to PIM generation in printed circuits. Finally, it is demonstrated that the electrical discontinuities can have significant effect on the overall PIM response of the distributed passive circuits and cause PIM product leakage and parasitic coupling between isolated circuit elements.
Resumo:
Wearable devices performing advanced bio-signal analysis algorithms are aimed to foster a revolution in healthcare provision of chronic cardiac diseases. In this context, energy efficiency is of paramount importance, as long-term monitoring must be ensured while relying on a tiny power source. Operating at a scaled supply voltage, just above the threshold voltage, effectively helps in saving substantial energy, but it makes circuits, and especially memories, more prone to errors, threatening the correct execution of algorithms. The use of error detection and correction codes may help to protect the entire memory content, however it incurs in large area and energy overheads which may not be compatible with the tight energy budgets of wearable systems. To cope with this challenge, in this paper we propose to limit the overhead of traditional schemes by selectively detecting and correcting errors only in data highly impacting the end-to-end quality of service of ultra-low power wearable electrocardiogram (ECG) devices. This partition adopts the protection of either significant words or significant bits of each data element, according to the application characteristics (statistical properties of the data in the application buffers), and its impact in determining the output. The proposed heterogeneous error protection scheme in real ECG signals allows substantial energy savings (11% in wearable devices) compared to state-of-the-art approaches, like ECC, in which the whole memory is protected against errors. At the same time, it also results in negligible output quality degradation in the evaluated power spectrum analysis application of ECG signals.
Resumo:
Esta tese investiga a caracterização (e modelação) de dispositivos que realizam o interface entre os domínios digital e analógico, tal como os buffers de saída dos circuitos integrados (CI). Os terminais sem fios da atualidade estão a ser desenvolvidos tendo em vista o conceito de rádio-definido-por-software introduzido por Mitola. Idealmente esta arquitetura tira partido de poderosos processadores e estende a operação dos blocos digitais o mais próximo possível da antena. Neste sentido, não é de estranhar que haja uma crescente preocupação, no seio da comunidade científica, relativamente à caracterização dos blocos que fazem o interface entre os domínios analógico e digital, sendo os conversores digital-analógico e analógico-digital dois bons exemplos destes circuitos. Dentro dos circuitos digitais de alta velocidade, tais como as memórias Flash, um papel semelhante é desempenhado pelos buffers de saída. Estes realizam o interface entre o domínio digital (núcleo lógico) e o domínio analógico (encapsulamento dos CI e parasitas associados às linhas de transmissão), determinando a integridade do sinal transmitido. Por forma a acelerar a análise de integridade do sinal, aquando do projeto de um CI, é fundamental ter modelos que são simultaneamente eficientes (em termos computacionais) e precisos. Tipicamente a extração/validação dos modelos para buffers de saída é feita usando dados obtidos da simulação de um modelo detalhado (ao nível do transístor) ou a partir de resultados experimentais. A última abordagem não envolve problemas de propriedade intelectual; contudo é raramente mencionada na literatura referente à caracterização de buffers de saída. Neste sentido, esta tese de Doutoramento foca-se no desenvolvimento de uma nova configuração de medição para a caracterização e modelação de buffers de saída de alta velocidade, com a natural extensão aos dispositivos amplificadores comutados RF-CMOS. Tendo por base um procedimento experimental bem definido, um modelo estado-da-arte é extraído e validado. A configuração de medição desenvolvida aborda não apenas a integridade dos sinais de saída mas também do barramento de alimentação. Por forma a determinar a sensibilidade das quantias estimadas (tensão e corrente) aos erros presentes nas diversas variáveis associadas ao procedimento experimental, uma análise de incerteza é também apresentada.
Resumo:
Embedding a double barrier resonant tunnelling diode (RTD) in a unipolar InGaAlAs optical waveguide gives rise to a very low driving voltage electroabsorption modulator (EAM) at optical wavelengths around 1550 nm. The presence of the RTD within the waveguide core introduces high non- linearity and negative di erential resistance in the current±voltage (I±V) characteristic of the waveguide. This makes the electric ®eld distribution across the waveguide core strongly dependent on the bias voltage: when the current decreases from the peak to the valley, there is an increase of the electric ®eld across the depleted core. The electric ®eld enhancement in the core-depleted layer causes the Franz±Keldysh absorption band-edge to red shift, which is responsible for the electroabsorption e ect. High-frequency ac signals as low as 100mV can induce electric ®eld high-speed switching, producing substantial light modulation (up to 15 dB) at photon energies slightly lower than the waveguide core band-gap energy. The key di erence between this device and conventional p-i-n EAMs is that the tunnelling characteristics of the RTD are employed to switch the electric ®eld across the core-depleted region; the RTD- EAM has in essence an integrated electronic ampli®er and, therefore, requires considerably less switching power.
Resumo:
This is a list of the courts in all the circuits of South Carolina and the percentage of cases disposed of in 365 day or less. None of the courts met the 80% benchmark.
Resumo:
This is a list of the courts in all the circuits of South Carolina and the percentage of cases disposed of in 365 day or less as of August 31, 2014. None of the courts met the 80% benchmark.