952 resultados para Hardware reconfigurável


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This paper proposes a novel hybrid forward algorithm (HFA) for the construction of radial basis function (RBF) neural networks with tunable nodes. The main objective is to efficiently and effectively produce a parsimonious RBF neural network that generalizes well. In this study, it is achieved through simultaneous network structure determination and parameter optimization on the continuous parameter space. This is a mixed integer hard problem and the proposed HFA tackles this problem using an integrated analytic framework, leading to significantly improved network performance and reduced memory usage for the network construction. The computational complexity analysis confirms the efficiency of the proposed algorithm, and the simulation results demonstrate its effectiveness

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Maximakinin is an N-terminally extended bradykinin (DLPKINRKGPRPPGFSPFR) from the venom of a Chinese toad (Bombina maxima) that displays highly selective activity at mammalian arterial smooth muscle receptors. In this study, we report that incubation of maximakinin with either kallikrein or human saliva generates catabolites with enhanced bioactivity that retain the tissue selective effects of the parent molecule. In addition, we have observed that kallikrein rapidly cleaves the C-terminal arginyl residue of both maximakinin and bradykinin – a cleavage hitherto considered to be performed by a carboxypeptidase that facilitates selective bradykinin receptor targeting. Maximakinin has thus evolved as a `smart' defensive weapon in the toad with inherent resistance to the signal-terminating protease hardware in the potential predator. Thus, natural selection of amphibian skin peptides for antipredator defence, through interspecies delivery by an exogenous secretory mode, produces subtle structural stabilization modifications that can potentially provide new insights for the design of orally active and selectively targeted peptide therapeutics.

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Paper describes an effcicient approach for provisioning of network resources based on SLAs and a range of negotiating agents. The work arose from direct collboration with Fujitsu research and invlolved a worldwide press reslease of their agent brokering system which was based on this; also, a plenary address: A.Marshall (QUB) & A.Campbell (Columbia, USA) at 4th IFIP/IEEE International conference on Management of Multimedia Networks and Services' 2001 (MMNS'01). ISSN: 0926-6801

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A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modem communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.