Highly efficient, limited range multipliers for LUT-based FPGA architectures
| Data(s) |
01/10/2004
|
|---|---|
| Identificador |
http://dx.doi.org/10.1109/TVLSI.2004.833399 http://www.scopus.com/inward/record.url?scp=6344229354&partnerID=8YFLogxK |
| Idioma(s) |
eng |
| Direitos |
info:eu-repo/semantics/restrictedAccess |
| Fonte |
Turner , R & Woods , R 2004 , ' Highly efficient, limited range multipliers for LUT-based FPGA architectures ' IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol 12(10) , no. 10 , pp. 1113-1118 . DOI: 10.1109/TVLSI.2004.833399 |
| Palavras-Chave | #/dk/atira/pure/subjectarea/asjc/1700/1708 #Hardware and Architecture #/dk/atira/pure/subjectarea/asjc/2200/2208 #Electrical and Electronic Engineering |
| Tipo |
article |
