A direct-conversion mixer with DC-offset cancellation for IEEE 802.11a WLAN receiver

A DC-offset cancellation scheme in the 5GHz direct-conversion receiver compliant with IEEE 802.11a wireless LAN standard is described in this paper. It uses the analog feedback loop to eliminate the DC-offset at the output of the double-balanced mixer. The mixer has a simulation voltage conversion gain of IMB at 5.2GHz, noise figure of 9.67dB, IIP3 of 7.6dBm. The solution provides 39.1dB reduction according to the leakage value at LO and mixer load resistors, the additional noise figure added to mixer is less than 0.9dB, the added power dissipation is 0.1mW and was fabricated in 60GHz 0.35 mu m SiGe BiCMOS technology.

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

Experiment on Qinghai-Tibet railroad subgrade temperature monitoring based on FBG sensors

Qinghai-Tibet Railway is the longest and highest plateau railway in the world. A long term monitoring system of the stability of the subgrade in the permafrost regions should be put forward immediately to prevent damage to the railway. As it's very difficult to set up the long-distance automatic monitoring system which contains a lot of measure points along the 550 kilometers railway in the permafrost area, we present a subgrade temperature monitor system based on fiber Bragg grating (FBG). In this paper the principles of the FBG was presented, and the feasibility of the FBG sensors in the permafrost area of Qinghai-Tibet plateau was analysized. We embedded fifteen FBG temperature sensors and thermal resistance temperature sensors. A contrast experiment is made while the two kinds of sensors are arranged in the same position. The result of the experiment shows that the accuracy of the FBG temperature sensors is less than 0.1 degrees C. and the FBG sensors can do well in the measurement of pattern which the temperature varies with the depth of the permafrost soil. The result also shows the stability of the FBG sensors in the bad environmental condition of Qinghai-Tibet plateau, which proves the feasibility of the application of FBG sensors and our monitoring system on the Qinghai-Tibet railway.

A high-gain high-linearity wide-band low noise amplifier for terrestrial and cable receptions

This paper presents the design of a wide-band low-noise amplifier (LNA) implemented in a 0.35 mu m SiGe BiCMOS technology for cable (DVB-C) and terrestrial (DVB-T) tuner applications. The LNA utilizes current injection to achieve high linearity. Without using inductors, the LNA achieves 0.1-1GHz wide bandwidth and 18.8-dB gain with less than 1.4-dB gain variation. The noise figure(NF) of the wideband LNA is 5dB, its 1-dB compression point is -2dBm and IIP3 is 8dBm. The LNA dissipates 120mW power with a 5-V supply.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.