A framework for fault tolerant real time systems based on reconfigurable FPGAs

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

On-line defragmentation for run-time partially reconfigurable FPGAs

Dynamically reconfigurable systems have benefited from a new class of FPGAs recently introduced into the market, which allow partial and dynamic reconfiguration at run-time, enabling multiple independent functions from different applications to share the same device, swapping resources as needed. When the sequence of tasks to be performed is not predictable, resource allocation decisions have to be made on-line, fragmenting the FPGA logic space. A rearrangement may be necessary to get enough contiguous space to efficiently implement incoming functions, to avoid spreading their components and, as a result, degrading their performance. This paper presents a novel active replication mechanism for configurable logic blocks (CLBs), able to implement on-line rearrangements, defragmenting the available FPGA resources without disturbing those functions that are currently running.

Controlo de um robô autónomo através de redes neuronais

Neste trabalho pretende-se introduzir os conceitos associados às redes neuronais e a sua aplicação no controlo de sistemas, neste caso na área da robótica autónoma. Foi utilizado um AGV de modo a testar experimentalmente um controlo através de uma rede neuronal artificial. A grande vantagem das redes neuronais artificiais é estas poderem ser ensinadas a funcionarem como se pretende. A partir desta caraterística foram efetuadas duas abordagens na implementação do AGV disponibilizado. A primeira abordagem ensinava a rede neuronal a funcionar como o controlo por lógica difusa que foi implementado no AGV aquando do seu desenvolvimento. A segunda abordagem foi ensinar a rede neuronal artificial a funcionar a partir de dados retirados de um controlo remoto simples implementado no AGV. Ambas as abordagens foram inicialmente implementadas e simuladas no MATLAB, antes de se efetuar a sua implementação no AGV. O MATLAB é utilizado para efetuar o treino das redes neuronais multicamada proactivas através do algoritmo de treino por retropropagação de Levenberg-Marquardt. A implementação de uma rede neuronal artificial na primeira abordagem foi implementada em três fases, MATLAB, posteriormente linguagem de programação C no computador e por fim, microcontrolador PIC no AGV, permitindo assim diferenciar o desenvolvimento destas técnicas em várias plataformas. Durante o desenvolvimento da segunda abordagem foi desenvolvido uma aplicação Android que permite monitorizar e controlar o AGV remotamente. Os resultados obtidos pela implementação da rede neuronal a partir do controlo difuso e do controlo remoto foram satisfatórios, pois o AGV percorria os percursos testados corretamente, em ambos os casos. Por fim concluiu-se que é viável a aplicação das redes neuronais no controlo de um AGV. Mais ainda, é possível utilizar o sistema desenvolvido para implementar e testar novas RNA.

JPEG decoder implementation on FPGA using dynamic partial reconfiguration

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e telecomunicações

Optimal fuzzy PID control tuned with genetic algorithms

Fuzzy logic controllers (FLC) are intelligent systems, based on heuristic knowledge, that have been largely applied in numerous areas of everyday life. They can be used to describe a linear or nonlinear system and are suitable when a real system is not known or too difficult to find their model. FLC provide a formal methodology for representing, manipulating and implementing a human heuristic knowledge on how to control a system. These controllers can be seen as artificial decision makers that operate in a closed-loop system, in real time. The main aim of this work was to develop a single optimal fuzzy controller, easily adaptable to a wide range of systems – simple to complex, linear to nonlinear – and able to control all these systems. Due to their efficiency in searching and finding optimal solution for high complexity problems, GAs were used to perform the FLC tuning by finding the best parameters to obtain the best responses. The work was performed using the MATLAB/SIMULINK software. This is a very useful tool that provides an easy way to test and analyse the FLC, the PID and the GAs in the same environment. Therefore, it was proposed a Fuzzy PID controller (FL-PID) type namely, the Fuzzy PD+I. For that, the controller was compared with the classical PID controller tuned with, the heuristic Ziegler-Nichols tuning method, the optimal Zhuang-Atherton tuning method and the GA method itself. The IAE, ISE, ITAE and ITSE criteria, used as the GA fitness functions, were applied to compare the controllers performance used in this work. Overall, and for most systems, the FL-PID results tuned with GAs were very satisfactory. Moreover, in some cases the results were substantially better than for the other PID controllers. The best system responses were obtained with the IAE and ITAE criteria used to tune the FL-PID and PID controllers.