Proposal for Graphene-Boron Nitride Heterobilayer-Based Tunnel FET

We investigate the gate-controlled direct band-to-band tunneling (BTBT) current in a graphene-boron nitride (G-BN) heterobilayer channel-based tunnel field effect transistor. We first study the imaginary band structure of hexagonal and Bernal-stacked heterobilayers by density functional theory, which is then used to evaluate the gate-controlled current under the Wentzel-Kramers-Brillouin approximation. It is shown that the direct BTBT is probable for a certain interlayer spacing of the G-BN which depends on the stacking orders.

Asynchronous Measurement of Transient Phase-Shift Resulting From RF Receiver State-Change

In a wireless receiver, a down-converted RF signal undergoes a transient phase shift, when the gain state is changed to adjust for varying conditions in transmission and propagation. A method is developed, in which such phase shifts are detected asynchronously, and their undesirable effects on the bit error rate are corrected. The method was developed for and used in, the system-level characterization and calibration of a 65-nm CMOS UHF receiver. The phase-shifts associated with specific gain-state transitions were measured within a test framework, and used in the baseband signal processing blocks to compensate for errors, whenever the receiver anticipated a gain-state transition.

Signal Detection in Generalized Gaussian Noise by Nonlinear Wavelet Denoising

In this paper, a nonlinear suboptimal detector whose performance in heavy-tailed noise is significantly better than that of the matched filter is proposed. The detector consists of a nonlinear wavelet denoising filter to enhance the signal-to-noise ratio, followed by a replica correlator. Performance of the detector is investigated through an asymptotic theoretical analysis as well as Monte Carlo simulations. The proposed detector offers the following advantages over the optimal (in the Neyman-Pearson sense) detector: it is easier to implement, and it is more robust with respect to error in modeling the probability distribution of noise.

A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applications

A power scalable receiver architecture is presented for low data rate Wireless Sensor Network (WSN) applications in 130nm RF-CMOS technology. Power scalable receiver is motivated by the ability to leverage lower run-time performance requirement to save power. The proposed receiver is able to switch power settings based on available signal and interference levels while maintaining requisite BER. The Low-IF receiver consists of Variable Noise and Linearity LNA, IQ Mixers, VGA, Variable Order Complex Bandpass Filter and Variable Gain and Bandwidth Amplifier (VGBWA) capable of driving variable sampling rate ADC. Various blocks have independent power scaling controls depending on their noise, gain and interference rejection (IR) requirements. The receiver is designed for constant envelope QPSK-type modulation with 2.4GHz RF input, 3MHz IF and 2MHz bandwidth. The chip operates at 1V Vdd with current scalable from 4.5mA to 1.3mA and chip area of 0.65mm2.

Comparison of OpAmp based and comparator based switched capacitor filter

Comparator based switched capacitor circuits provide an excellent opportunity to design sampled data systems where the virtual ground condition is detected rather than being continuously forced with negative feedback in Opamp based circuits. This work is an application of this concept to design a 1 st order 330 KHz cutoff frequency Lowpass filter operating at 10 MHz sampling frequency in 0.13μm technology and 1.2 V supply voltage. The Comparator Based Switched Capacitor (CBSC) filter is compared with conventional Two stage Miller compensated Operational amplifier based switched capacitor filter. It is shown that CBSC filter relaxes the constraints like speed ,linearity, gain, stability which would otherwise be hard to satisfy in scaled technologies in Opamp based circuits. The designed CBSC based lowpass filter provides significant power savings compared to traditional Opamp based switched capacitor filter.

Design Of Start-up Power Circuit For Control Power Supplies With Wide Input Voltage Variation

This paper presents the design of a start up power circuit for a control power supply (CPS) which feeds power to the sub-systems of High Power Converters (HPC). The sub-systems such as gate drive card, annunciation card, protection and delay card etc; needs to be provided power for the operation of a HPC. The control power supply (CPS) is designed to operate over a wide range of input voltage from 90Vac to 270Vac. The CPS output supplies power at a desired voltage of Vout =24V to the auxiliary sub-systems of the HPC. During the starting, the power supply to the control circuitry of CPS in turn, is obtained using a separate start-up power supply. This paper discusses the various design issues of the start-up power circuit to ensure that start-up and shut down of the CPS occurs reliably. The CPS also maintains the power factor close to unity and low total harmonic distortion in input current. The paper also provides design details of gate drive circuits employed for the CPS as well as the design of on-board power supply for the CPS. Index terms: control power supply, start-up power supply, DSFC, pre-regulator

Functional analysis of ultra high information rates conveyed by rat vibrissal primary afferents

Sensory receptors determine the type and the quantity of information available for perception. Here, we quantified and characterized the information transferred by primary afferents in the rat whisker system using neural system identification. Quantification of ``how much'' information is conveyed by primary afferents, using the direct method (DM), a classical information theoretic tool, revealed that primary afferents transfer huge amounts of information (up to 529 bits/s). Information theoretic analysis of instantaneous spike-triggered kinematic stimulus features was used to gain functional insight on ``what'' is coded by primary afferents. Amongst the kinematic variables tested-position, velocity, and acceleration-primary afferent spikes encoded velocity best. The other two variables contributed to information transfer, but only if combined with velocity. We further revealed three additional characteristics that play a role in information transfer by primary afferents. Firstly, primary afferent spikes show preference for well separated multiple stimuli (i.e., well separated sets of combinations of the three instantaneous kinematic variables). Secondly, neurons are sensitive to short strips of the stimulus trajectory (up to 10 ms pre-spike time), and thirdly, they show spike patterns (precise doublet and triplet spiking). In order to deal with these complexities, we used a flexible probabilistic neuron model fitting mixtures of Gaussians to the spike triggered stimulus distributions, which quantitatively captured the contribution of the mentioned features and allowed us to achieve a full functional analysis of the total information rate indicated by the DM. We found that instantaneous position, velocity, and acceleration explained about 50% of the total information rate. Adding a 10 ms pre-spike interval of stimulus trajectory achieved 80-90%. The final 10-20% were found to be due to non-linear coding by spike bursts.

Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13-mu m CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.

Temperature and potential dependence electrochemical impedance studies of LiMn2O4

Detailed analysis of alternating current impedance data of LiMn2O4 electrodes measured at several temperatures and potentials was carried out. The Nyquist plots generally consisted of semicircles corresponding to two time constants. However, at low temperatures (-10 to 10 A degrees C) and potential region between 3.90 and 4.20 V, three time constants were present. The third semicircle present at the middle to high frequency range was attributed to electronic resistance of LiMn2O4. Impedance parameters were evaluated using appropriate electrical equivalent circuits. From the temperature dependence of resistive parameters, activation energy values for the corresponding processes were calculated.

Using an Office Inkjet Printer to Define the Formation of Copper Films on Paper

A low-cost fabrication process for forming conductive copper lines on paper is presented. An office inkjet printer was used to deposit desired patterns of silver nitrate and tannic acid solutions sequentially on paper. Silver nitrate was instantaneously reduced in situ on paper by tannic acid at room temperature to form silver nanoparticles, which acted as catalysts for the subsequent electroless deposition of copper. The copper films were 1.8 mu m thick, and the sheet resistance of the copper film on paper was 9 Omega/square. A dual monopole ultrawide band antenna was fabricated on paper and its performance was equivalent to that of a similar antenna fabricated on a copper-film covered Kapton substrate using conventional lithographic processes. The paper-based conductive copper films fabricated using the facile process presented herein will aid the development of low-cost flexible circuits and sensors.

Characterization and Performance Study of Packaged Micropump for Drug Delivery

In this work, we present the characterization and performance studies of self-priming peristaltic pump for drug delivery application. Conventional materials and methods have been used to fabricate single cam mechanism based peristaltic micropump. To control the fluid flow precisely in micro liter range, a single cam mechanism has been used instead of conventional roller mechanism. The fabricated pump is suitable for liquid, gas and foam. Using water as a fluid medium, a flow rate of 12.5 mu l/rpm is achieved using a flexible silicone tube of inner diameter 1.5 mm and outer diameter 2.5 mm. Other than water, higher viscosity fluids showed a decrease in the flow rate. The designed micropump exhibits a linear dependence of flow rate in the voltage range of 2.5V to 5V. Drug delivery using micropump demands that the micropump has to pump against the blood pressure (maximum of 25kPa) with constant flow rate. Here the designed pump is able to pump the liquid with a constant flow rate of 500 mu l/min (water) up to a backpressure of 40kPa. It was observed that, by increasing the backpressure above 40kPa, flow rate of the pump gradually decreased to 125 mu l/min at 120kPa. In addition, Micropump based drug delivery demands that the micropump should be normally in closed condition in all the positions to avoid drug leakage and bleeding. Hence, micropump has been characterized for normally closed condition in all positions (0 degrees to 360 degrees). However, a minute leak of 0.14 % was found for an inlet pressure of 140kPa. Also, the normally closed region with no leak is observed up to 60kPa of pressure in all positions (0 degrees to 360 degrees).

Packaging of Polyvinylidene fluoride nasal sensor for biomedical applications

This paper presents the design technique that has been adopted for packaging of Polyvinylidene fluoride (PVDF) nasal sensor for biomedical applications. The PVDF film with the dimension of length 10mm, width 5mm and thickness 28 mu m was firmly adhered on one end of plastic base (8mmx5mmx30 mu m) in such a way that it forms a cantilever configuration leaving the other end free for deflection. Now with the leads attached on the surface of the PVDF film, the cantilever configuration becomes the PVDF nasal sensor. For mounting a PVDF nasal sensor, a special headphone was designed, that can fit most of the human head sizes. Two flexible strings are soldered on either side of the headphone. Two identical PVDF nasal sensors were then connected to either side of flexible string of the headphone in such a way that they are placed below the right and left nostrils respectively without disturbing the normal breathing. When a subject wares headphone along with PVDF nasal sensors, two voltage signals due to the piezoelectric property of the PVDF film were generated corresponding to his/her nasal airflow from right and left nostril. The entire design was made compact, so that PVDF nasal sensors along with headphone can be made portable. No special equipment or machines are needed for mounting the PVDF nasal sensors. The time required for packaging of PVDF nasal sensors was less and the approximate cost of the entire assembly (PVDF nasal sensors + headphone) was very nominal.

High Throughput, Low Latency, Memory Optimized 64K Point FFT Architecture using Novel Radix-4 Butterfly Unit

In this paper we propose a fully parallel 64K point radix-4(4) FFT processor. The radix-4(4) parallel unrolled architecture uses a novel radix-4 butterfly unit which takes all four inputs in parallel and can selectively produce one out of the four outputs. The radix-4(4) block can take all 256 inputs in parallel and can use the select control signals to generate one out of the 256 outputs. The resultant 64K point FFT processor shows significant reduction in intermediate memory but with increased hardware complexity. Compared to the state-of-art implementation 5], our architecture shows reduced latency with comparable throughput and area. The 64K point FFT architecture was synthesized using a 130nm CMOS technology which resulted in a throughput of 1.4 GSPS and latency of 47.7 mu s with a maximum clock frequency of 350MHz. When compared to 5], the latency is reduced by 303 mu s with 50.8% reduction in area.

Influence of O-2 flow rate on HfO2 gate dielectrics for back-gated graphene transistors

HfO2 thin films deposited on Si substrate using electron beam evaporation, are evaluated for back-gated graphene transistors. The amount of O-2 flow rate, during vaporation is optimized for 35 nm thick HfO2 films, to achieve the best optical, chemical and electrical properties. It has been observed that with increasing oxygen flow rate, thickness of the films increased and refractive index decreased due to increase in porosity resulting from the scattering of the evaporant. The films deposited at low O-2 flow rates (1 and 3 SCCM) show better optical and compositional properties. The effects of post-deposition annealing and post-metallization annealing in forming gas ambience (FGA) on the optical and electrical properties of the films have been analyzed. The film deposited at 3 SCCM O-2 flow rate shows the best properties as measured on MOS capacitors. To evaluate the performance of device properties, back-gated bilayer graphene transistors on HfO2 films deposited at two O-2 flow rates of 3 and 20 SCCM have been fabricated and characterized. The transistor with HfO2 film deposited at 3 SCCM O-2 flow rate shows better electrical properties consistent with the observations on MOS capacitor structures. This suggests that an optimum oxygen pressure is necessary to get good quality films for high performance devices.

AIM-Spice Integration of a Recursive Model for Threshold Voltage Shift in Thin Film Transistors

Non-crystalline semiconductor based thin film transistors are the building blocks of large area electronic systems. These devices experience a threshold voltage shift with time due to prolonged gate bias stress. In this paper we integrate a recursive model for threshold voltage shift with the open source BSIM4V4 model of AIM-Spice. This creates a tool for circuit simulation for TFTs. We demonstrate the integrity of the model using several test cases including display driver circuits.