Raman Spectroscopy and DFT calculations for the Electronic Structure Characterization of Conjugated Polymers

In the last three decades, there has been a broad academic and industrial interest in conjugated polymers as semiconducting materials for organic electronics. Their applications in polymer light-emitting diodes (PLEDs), polymer solar cells (PSCs), and organic field-effect transistors (OFETs) offer opportunities for the resolution of energy issues as well as the development of display and information technologies1. Conjugated polymers provide several advantages including low cost, light weight, good flexibility, as well as solubility which make them readily processed and easily printed, removing the conventional photolithography for patterning2. A large library of polymer semiconductors have been synthesized and investigated with different building blocks, such as acenes or thiophene and derivatives, which have been employed to design new materials according to individual demands for specific applications. To design ideal conjugated polymers for specific applications, some general principles should be taken into account, including (i) side chains (ii) molecular weights, (iii) band gap and HOMO and LUMO energy levels, and (iv) suited morphology.3-6 The aim of this study is to elucidate the impact that substitution exerts on the molecular and electronic structure of π-conjugated polymers with outstanding performances in organic electronic devices. Different configurations of the π-conjugated backbones are analyzed: (i) donor-acceptor configuration, (ii) 1D lineal or 2D branched conjugated backbones, and (iii) encapsulated polymers (see Figure 1). Our combined vibrational spectroscopy and DFT study shows that small changes in the substitution pattern and in the molecular configuration have a strong impact on the electronic characteristics of these polymers. We hope this study can advance useful structure-property relationships of conjugated polymers and guide the design of new materials for organic electronic applications.

Electrical characterization of electronic circuits produced by inkjet printing

Dissertação de Mestrado, Engenharia Electrónica e Telecomunicações, Faculdade de Ciências e Tecnologia, Universidade do Algarve, 2014

Applications of electrospun nanofibers for electronic devices

In recent decades, electrospinning of nanofibers has progressed very rapidly in both scientific and technological aspects, and electrospun nanofibers have shown enormous potential for various applications. In particular, electrospun nanofibers have significantly enhanced the application performance of many electronic devices, such as solar cells, mechanical-to-electric energy harvesters, rechargeable batteries, supercapacitors, sensors, field-effect transistors, diodes, photodetectors, and electrochromic devices. This chapter provides a comprehensive summary on the recent progress in the application of electrospun nanofibers in electronic devices.

Leakage Temperature Dependency Aware Real-Time Scheduling for Power and Thermal Optimization

Catering to society’s demand for high performance computing, billions of transistors are now integrated on IC chips to deliver unprecedented performances. With increasing transistor density, the power consumption/density is growing exponentially. The increasing power consumption directly translates to the high chip temperature, which not only raises the packaging/cooling costs, but also degrades the performance/reliability and life span of the computing systems. Moreover, high chip temperature also greatly increases the leakage power consumption, which is becoming more and more significant with the continuous scaling of the transistor size. As the semiconductor industry continues to evolve, power and thermal challenges have become the most critical challenges in the design of new generations of computing systems. In this dissertation, we addressed the power/thermal issues from the system-level perspective. Specifically, we sought to employ real-time scheduling methods to optimize the power/thermal efficiency of the real-time computing systems, with leakage/ temperature dependency taken into consideration. In our research, we first explored the fundamental principles on how to employ dynamic voltage scaling (DVS) techniques to reduce the peak operating temperature when running a real-time application on a single core platform. We further proposed a novel real-time scheduling method, “M-Oscillations” to reduce the peak temperature when scheduling a hard real-time periodic task set. We also developed three checking methods to guarantee the feasibility of a periodic real-time schedule under peak temperature constraint. We further extended our research from single core platform to multi-core platform. We investigated the energy estimation problem on the multi-core platforms and developed a light weight and accurate method to calculate the energy consumption for a given voltage schedule on a multi-core platform. Finally, we concluded the dissertation with elaborated discussions of future extensions of our research.

System-on-a-Chip (SoC) based Hardware Acceleration in Register Transfer Level (RTL) Design

Today, modern System-on-a-Chip (SoC) systems have grown rapidly due to the increased processing power, while maintaining the size of the hardware circuit. The number of transistors on a chip continues to increase, but current SoC designs may not be able to exploit the potential performance, especially with energy consumption and chip area becoming two major concerns. Traditional SoC designs usually separate software and hardware. Thus, the process of improving the system performance is a complicated task for both software and hardware designers. The aim of this research is to develop hardware acceleration workflow for software applications. Thus, system performance can be improved with constraints of energy consumption and on-chip resource costs. The characteristics of software applications can be identified by using profiling tools. Hardware acceleration can have significant performance improvement for highly mathematical calculations or repeated functions. The performance of SoC systems can then be improved, if the hardware acceleration method is used to accelerate the element that incurs performance overheads. The concepts mentioned in this study can be easily applied to a variety of sophisticated software applications. The contributions of SoC-based hardware acceleration in the hardware-software co-design platform include the following: (1) Software profiling methods are applied to H.264 Coder-Decoder (CODEC) core. The hotspot function of aimed application is identified by using critical attributes such as cycles per loop, loop rounds, etc. (2) Hardware acceleration method based on Field-Programmable Gate Array (FPGA) is used to resolve system bottlenecks and improve system performance. The identified hotspot function is then converted to a hardware accelerator and mapped onto the hardware platform. Two types of hardware acceleration methods – central bus design and co-processor design, are implemented for comparison in the proposed architecture. (3) System specifications, such as performance, energy consumption, and resource costs, are measured and analyzed. The trade-off of these three factors is compared and balanced. Different hardware accelerators are implemented and evaluated based on system requirements. 4) The system verification platform is designed based on Integrated Circuit (IC) workflow. Hardware optimization techniques are used for higher performance and less resource costs. Experimental results show that the proposed hardware acceleration workflow for software applications is an efficient technique. The system can reach 2.8X performance improvements and save 31.84% energy consumption by applying the Bus-IP design. The Co-processor design can have 7.9X performance and save 75.85% energy consumption.

Development and characterisation of solution processed vanadium oxide and transparent metal oxide thin films

Metal oxide thin films are important for modern electronic devices ranging from thin film transistors to photovoltaics and functional optical coatings. Solution processed techniques allow for thin films to be rapidly deposited over a range of surfaces without the extensive processing of comparative vapour or physical deposition methods. The production of thin films of vanadium oxide prepared through dip-coating was developed enabling a greater understanding of the thin film formation. Mechanisms of depositing improved large area uniform coverage on a number of technologically relevant substrates were examined. The fundamental mechanism for polymer-assisted deposition in improving thin film surface smoothness and long range order has been delivered. Different methods were employed for adapting the alkoxide based dip-coating technique to produce a variety of amorphous and crystalline vanadium oxide based thin films. Using a wide range of material, spectroscopic and optical measurement techniques the morphology, structure and optoelectronic properties of the thin films were studied. The formation of pinholes on the surface of the thin films, due to dewetting and spinodal effects, was inhibited using the polymer assisted deposition technique. Uniform thin films with sub 50 nm thicknesses were deposited on a variety of substrates controlled through alterations to the solvent-alkoxide dilution ratios and employing polymer assisted deposition techniques. The effects of polymer assisted deposition altered the crystallized VO thin films from a granular surface structure to a polycrystalline structure composed of high density small in-plane grains. The formation of transparent VO based thin film through Si and Na substrate mediated diffusion highlighted new methods for material formation and doping.

Modifying the band gap and optical properties of Germanium nanowires by surface termination

Semiconductor nanowires, based on silicon (Si) or germanium (Ge) are leading candidates for many ICT applications, including next generation transistors, optoelectronics, gas and biosensing and photovoltaics. Key to these applications is the possibility to tune the band gap by changing the diameter of the nanowire. Ge nanowires of different diameter have been studied with H termination, but, using ideas from chemistry, changing the surface terminating group can be used to modulate the band gap. In this paper we apply the generalised gradient approximation of density functional theory (GGA-DFT) and hybrid DFT to study the effect of diameter and surface termination using –H, –NH2 and –OH groups on the band gap of (001), (110) and (111) oriented germanium nanowires. We show that the surface terminating group allows both the magnitude and the nature of the band gap to be changed. We further show that the absorption edge shifts to longer wavelength with the –NH2 and –OH terminations compared to the –H termination and we trace the origin of this effect to valence band modifications upon modifying the nanowire with –NH2 or –OH. These results show that it is possible to tune the band gap of small diameter Ge nanowires over a range of ca. 1.1 eV by simple surface chemistry.

Carrier momentum relaxation in highly doped polar semiconductors and semiconductor heterostructures

Highly doped polar semiconductors are essential components of today’s semiconductor industry. Most strikingly, transistors in modern electronic devices are polar semiconductor heterostructures. It is important to thoroughly understand carrier transport in such structures. In doped polar semiconductors, collective excitations of the carriers (plasmons) and the atoms (polar phonons) couple. These coupled collective excitations affect the electrical conductivity, here quantified through the carrier mobility. In scattering events, the carriers and the coupled collective modes transfer momentum between each other. Carrier momentum transferred to polar phonons can be lost to other phonons through anharmonic decay, resulting in a finite carrier mobility. The plasmons do not have a decay mechanism which transfers carrier momentum irretrievably. Hence, carrier-plasmon scattering results in infinite carrier mobility. Momentum relaxation due to either carrier–plasmon scattering or carrier–polar-phonon scattering alone are well understood. However, only this thesis manages to treat momentum relaxation due to both scattering mechanisms on an equal footing, enabling us to properly calculate the mobility limited by carrier–coupled plasmon–polar phonon scattering. We achieved this by solving the coupled Boltzmann equations for the carriers and the collective excitations, focusing on the “drag” term and on the anharmonic decay process of the collective modes. Our approach uses dielectric functions to describe both the carrier-collective mode scattering and the decay of the collective modes. We applied our method to bulk polar semiconductors and heterostructures where various polar dielectrics surround a semiconducting monolayer of MoS2, where taking plasmons into account can increase the mobility by up to a factor 15 for certain parameters. This screening effect is up to 85% higher than if calculated with previous methods. To conclude, our approach provides insight into the momentum relaxation mechanism for carrier–coupled collective mode scattering, and better tools for calculating the screened polar phonon and interface polar phonon limited mobility.

Implementation of dual stack technique for reducing leakage and dynamic power

This paper deals with proposal of a new dual stack approach for reducing both leakage and dynamic powers. The development of digital integrated circuits is challenged by higher power consumption. Thecombination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality ona chip. Scaling helps to increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Today leakage power has become anincreasingly important issue in processor hardware and software design. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The leakage power increases astechnology is scaled down. In this paper, we propose a new dual stack approach for reducing both leakage and dynamic powers. Moreover, the novel dual stack approach shows the least speed power product whencompared to the existing methods. All well known approach is “Sleep” in this method we reduce leakage power. The proposed Dual Stack approach we reduce more power leakage. Dual Stack approach uses theadvantage of using the two extra pull-up and two extra pull-down transistors in sleep mode either in OFF state or in ON state. Since the Dual Stack portion can be made common to all logic circuitry, less number of transistors is needed to apply a certain logic circuit.The dual stack approach shows the least speed power product among all methods. The Dual Stack technique provides new ways to designers who require ultra-low leakage power consumption with much less speedpower product.

Procesos hopping a través del modelo difusional en materiales nanocristalinos usados para aplicaciones fotovoltaicas

Se presentan los modelos de hopping de rango variable (variable range hopping; VRH), vecinos cercanos (nearest neighbor hopping; NNH) y barreras de potencial presentes en las fronteras de grano; como mecanismos de transporte eléctrico predominantes en los materiales semiconductores para aplicaciones fotovoltaicas. Las medidas de conductividad a oscuras en función de temperatura fueron realizadas para región de bajas temperaturas entre 120 y 400 K con Si y compuestos Cu3BiS2 y Cu2ZnSnSe4. Siguiendo la teoría de percolación, se obtuvieron parámetros hopping y la densidad de estados cerca del nivel de Fermi, N(EF), para todas las muestras. A partir de los planteamientos dados por Mott para VRH, se presentó el modelo difusional, que permitió establecer la relación entre la conductividad y la densidad de estados de defecto o estados localizados en el gap del material. El análisis comparativo entre modelos, evidenció, que es posible obtener mejora hasta de un orden de magnitud en valores para cada uno de los parámetros hopping que caracterizan el material.

HVDC Power Transmission Simulation for Offshore Wind System with Three-Level Converter

An integrated mathematical model for the simulation of an offshore wind system performance is presented in this paper. The mathematical model considers an offshore variable-speed turbine in deep water equipped with a permanent magnet synchronous generator using multiple point full-power clamped three-level converter, converting the energy of a variable frequency source in injected energy into the electric network with constant frequency, through a HVDC transmission submarine cable. The mathematical model for the drive train is a concentrate two mass model which incorporates the dynamic for the blades of the wind turbine, tower and generator due to the need to emulate the effects of the wind and the floating motion. Controller strategy considered is a proportional integral one. Also, pulse width modulation using space vector modulation supplemented with sliding mode is used for trigger the transistors of the converter. Finally, a case study is presented to access the system performance.