Three-phase, three-limb, steady-state transformer model

This paper presents the development and implementation of a digital simulation model of a threephase, three-leg, three-winding power transformer. The proposed model, implemented in MATLAB environment, is based on the simultaneous analysis of both magnetic and electric lumped-parameters equivalents circuits, and it is intended to study its adequacy to incorporate, at a later stage, the influences of the occurrence of windings interturn short-circuit faults. Both simulation and laboratory tests results, obtained so far, for a three-phase, 6 kVA transformer, demonstrate the adequacy of the model under normal operating conditions.

Training control centers' operators in incident diagnosis and power restoration using intelligent tutoring systems

The activity of Control Center operators is important to guarantee the effective performance of Power Systems. Operators’ actions are crucial to deal with incidents, especially severe faults like blackouts. In this paper, we present an Intelligent Tutoring approach for training Portuguese Control Center operators in tasks like incident analysis and diagnosis, and service restoration of Power Systems. Intelligent Tutoring System (ITS) approach is used in the training of the operators, having into account context awareness and the unobtrusive integration in the working environment. Several Artificial Intelligence techniques were criteriously used and combined together to obtain an effective Intelligent Tutoring environment, namely Multiagent Systems, Neural Networks, Constraint-based Modeling, Intelligent Planning, Knowledge Representation, Expert Systems, User Modeling, and Intelligent User Interfaces.

Proposta de um algoritmo eficiente para a localização de faltas por relé diferencial numérico para proteção de linhas de transmissão com compensação série controlada por tiristores (TCSC)

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Desenvolvimento de uma plataforma SIG para apoio ao estudo da sismicidade em Portugal

Trabalho Final de Mestrado elaborado no Laboratório Nacional de Engenharia Civil (LNEC) para a obtenção do grau de Mestre em Engenharia Civil pelo Instituto Superior de Engenharia de Lisboa no âmbito do protocolo de cooperação entre o ISEL e o LNEC

Diagnóstico de avarias em motores elétricos

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Mecânica

Estágio na empresa SPECMAN para a prática de técnicas de controlo da condição

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Mecânica

Aplicação de redes neuronais artificiais à deteção e isolamento de falhas em processos industriais

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Mecânica

Tool effects on hybrid laminates drilling

Fiber reinforced plastics are increasing their importance as one of the most interesting groups of material on account of their low weight, high strength, and stiffness. To obtain good quality holes, it is important to identify the type of material, ply stacking sequence, and fiber orientation. In this article, the drilling of quasi-isotropic hybrid carbon +glass/epoxy plates is analyzed. Two commercial drills and a special step drill are compared considering the thrust force and delamination extension. Results suggest that the proposed step drill can be a suitable option in laminate drilling.

Real time fault injection using enhanced OCD -- a performance analysis

Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

On-line self-healing of circuits implemented on reconfigurable FPGAs

To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radiation-induced faults, which affect values stored in memory cells, and to manufacturing imperfections. Fault tolerant implementations, based on Triple Modular Redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like module placement, the effects of multi- bit upsets (MBU) or fault accumulation, have also to be addressed. In case of a fault occurrence the correct operation of the affected module must be restored and/or the current state of the circuit coherently re-established. A solution that enables the autonomous restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in real-time, while keeping the normal operation of the circuit, is presented in this paper.

A framework for self-healing radiation-tolerant implementations on reconfigurable FPGAs

To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant implementations, based on triple modular redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like the effects of multi-bit upsets (MBU) or fault accumulation, have also to be addressed. Furthermore, in case of a fault occurrence the correct operation of the affected module must be restored and the current state of the circuit coherently re-established. A solution that enables the autonomous correct restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in realtime, while keeping the normal operation of the circuit, is presented in this paper.

Estudo de falha em placas laminadas usando métodos analíticos e numéricos

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Manutenção

Low-cost vibration sensors: tendencies and applications in condition monitoring of machines and structures

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia Mecânica

Assinatura tectono-sedimentar do auge da compressão bética em Portugal: a descontinuidade sedimentar Valesiano terminal-Turoliano

An Upper Miocene important sedimentary break can be accurately recognised in the Portuguese basins and is reflected by a drastic palaeogeographic change in relation to a large-scale tectonic event of probable uppermost Vallesian-Turolian (9,5 Ma; middle Tortonian) age. The characterisation of the sedimentary record of this tectonic event, as well as its relations with interpreted active faults is made for different situations: Douro (NW border), Mondego, Lower-Tagus and Sado Tertiary basins. The sedimentary record, considered upper Tortonian-Messinian ? (uppermost Vallesian-Turolian ?) is interpreted mainly as endorheic alluvial fans (internal drainage), developed along active NNE-SSW indent-linked strike-slip faults and NE-SW reverse faults. At NE Portugal, proximal fluvial systems of an endorheic hydrographic network drained eastwards to the Spanish Duero interior Basin. The main evidences of the betic compression clímax in Portugal mainland are presented; the interpreted active tectonic structures are in accordance with an intense NNW-SSE crustal shortening, but some regional differences are also documented.