A System-C based Micro architectural Exploration Framework for Latency, Power and Performance Trade-offs of On-Chip Interconnection

We describe a System-C based framework we are developing, to explore the impact of various architectural and microarchitectural level parameters of the on-chip interconnection network elements on its power and performance. The framework enables one to choose from a variety of architectural options like topology, routing policy, etc., as well as allows experimentation with various microarchitectural options for the individual links like length, wire width, pitch, pipelining, supply voltage and frequency. The framework also supports a flexible traffic generation and communication model. We provide preliminary results of using this framework to study the power, latency and throughput of a 4x4 multi-core processing array using mesh, torus and folded torus, for two different communication patterns of dense and sparse linear algebra. The traffic consists of both Request-Response messages (mimicing cache accesses)and One-Way messages. We find that the average latency can be reduced by increasing the pipeline depth, as it enables higher link frequencies. We also find that there exists an optimum degree of pipelining which minimizes energy-delay product.

Optimal Power and Noise for Analog and Digital Sections of a Low Power Radio Receiver

We determine the optimal allocation of power between the analog and digital sections of an RF receiver while meeting the BER constraint. Unlike conventional RF receiver designs, we treat the SNR at the output of the analog front end (SNRAD) as a design parameter rather than a specification to arrive at this optimal allocation. We first determine the relationship of the SNRAD to the resolution and operating frequency of the digital section. We then use power models for the analog and digital sections to solve the power minimization problem. As an example, we consider a 802.15.4 compliant low-IF receiver operating at 2.4 GHz in 0.13 μm technology with 1.2 V power supply. We find that the overall receiver power is minimized by having the analog front end provide an SNR of 1.3dB and the ADC and the digital section operate at 1-bit resolution with 18MHz sampling frequency while achieving a power dissipation of 7mW.

Best Node Selection Through Distributed Fast Variable Power Multiple Access

In many wireless applications, it is highly desirable to have a fast mechanism to resolve or select the packet from the user with the highest priority. Furthermore, individual priorities are often known only locally at the users. In this paper we introduce an extremely fast, local-information-based multiple access algorithm that selects the best node in 1.8 to 2.1 slots,which is much lower than the 2.43 slot average achieved by the best algorithm known to date. The algorithm, which we call Variable Power Multiple Access Selection (VP-MAS), uses the local channel state information from the accessing nodes to the receiver, and maps the priorities into the receive power.It is inherently distributed and scales well with the number of users. We show that mapping onto a discrete set of receive power levels is optimal, and provide a complete characterization for it. The power levels are chosen to exploit packet capture that inherently occurs in a wireless physical layer. The VP-MAS algorithm adjusts the expected number of users that contend in each step and their respective transmission powers, depending on whether previous transmission attempts resulted in capture,idle channel, or collision.

An Adaptive Feature Based Low Power Motion Estimation Algorithm

Motion Estimation is one of the most power hungry operations in video coding. While optimal search (eg. full search)methods give best quality, non optimal methods are often used in order to reduce cost and power. Various algorithms have been used in practice that trade off quality vs. complexity. Global elimination is an algorithm based on pixel averaging to reduce complexity of motion search while keeping performance close to that of full search. We propose an adaptive version of the global elimination algorithm that extracts individual macro-block features using Hadamard transform to optimize the search. Performance achieved is close to the full search method and global elimination. Operational complexity and hence power is reduced by 30% to 45% compared to global elimination method.

A low power, process invariant keeper design for high speed dynamic logic circuits

A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation in the domino gate by 70% compared to the conventional keeper technique. Also the total power-delay product is 26% lower compared to the previously reported techniques. The process tracking capability of the design enables the domino gate to achieve uniform delay across different process corners. This reduces the amount of short circuit power dissipation that occurs in the cascaded domino gates by 90%. The use of the proposed technique in the read path of a register file reduces the energy requirement by 26% as compared to the other keeper techniques. The proposed technique has been prototyped in 130nm CMOS technology.

Numerical Study Of Heat Transfer From Pin Fin Heat Sink Using Steady And Pulsated Impinging Jets

The work reported in this thesis is an attempt to enhance heat transfer in electronic devices with the use of impinging air jets on pin-finned heat sinks. The cooling per-formance of electronic devices has attracted increased attention owing to the demand of compact size, higher power densities and demands on system performance and re-liability. Although the technology of cooling has greatly advanced, the main cause of malfunction of the electronic devices remains overheating. The problem arises due to restriction of space and also due to high heat dissipation rates, which have increased from a fraction of a W/cm2to 100s of W /cm2. Although several researchers have at-tempted to address this at the design stage, unfortunately the speed of invention of cooling mechanism has not kept pace with the ever-increasing requirement of heat re- moval from electronic chips. As a result, efficient cooling of electronic chip remains a challenge in thermal engineering. Heat transfer can be enhanced by several ways like air cooling, liquid cooling, phase change cooling etc. However, in certain applications due to limitations on cost and weight, eg. air borne application, air cooling is imperative. The heat transfer can be increased by two ways. First, increasing the heat transfer coefficient (forced convec- tion), and second, increasing the surface area of heat transfer (finned heat sinks). From previous literature it was established that for a given volumetric air flow rate, jet im-pingement is the best option for enhancing heat transfer coefficient and for a given volume of heat sink material pin-finned heat sinks are the best option because of their high surface area to volume ratio. There are certain applications where very high jet velocities cannot be used because of limitations of noise and presence of delicate components. This process can further be improved by pulsating the jet. A steady jet often stabilizes the boundary layer on the surface to be cooled. Enhancement in the convective heat transfer can be achieved if the boundary layer is broken. Disruptions in the boundary layer can be caused by pulsating the impinging jet, i.e., making the jet unsteady. Besides, the pulsations lead to chaotic mixing, i.e., the fluid particles no more follow well defined streamlines but move unpredictably through the stagnation region. Thus the flow mimics turbulence at low Reynolds number. The pulsation should be done in such a way that the boundary layer can be disturbed periodically and yet adequate coolant is made available. So, that there is not much variation in temperature during one pulse cycle. From previous literature it was found that square waveform is most effective in enhancing heat transfer. In the present study the combined effect of pin-finned heat sink and impinging slot jet, both steady and unsteady, has been investigated for both laminar and turbulent flows. The effect of fin height and height of impingement has been studied. The jets have been pulsated in square waveform to study the effect of frequency and duty cycle. This thesis attempts to increase our understanding of the slot jet impingement on pin-finned heat sinks through numerical investigations. A systematic study is carried out using the finite-volume code FLUENT (Version 6.2) to solve the thermal and flow fields. The standard k-ε model for turbulence equations and two layer zonal model in wall function are used in the problem Pressure-velocity coupling is handled using the SIMPLE algorithm with a staggered grid. The parameters that affect the heat transfer coefficient are: height of the fins, total height of impingement, jet exit Reynolds number, frequency of the jet and duty cycle (percentage time the jet is flowing during one complete cycle of the pulse). From the studies carried out it was found that: a) beyond a certain height of the fin the rate of enhancement of heat transfer becomes very low with further increase in height, b) the heat transfer enhancement is much more sensitive to any changes at low Reynolds number than compared to high Reynolds number, c) for a given total height of impingement the use of fins and pulsated jet, increases the effective heat transfer coefficient by almost 200% for the same average Reynolds number, d) for all the cases it was observed that the optimum frequency of impingement is around 50 − 100 Hz and optimum duty cycle around 25-33.33%, e) in the case of turbulent jets the enhancement in heat transfer due to pulsations is very less compared to the enhancement in case of laminar jets.