Epitaxial growth of molecular crystals on van der Waals substrates for high-performance organic electronics

Epitaxial van der Waals (vdW) heterostructures of organic and layered materials are demonstrated to create high-performance organic electronic devices. High-quality rubrene films with large single-crystalline domains are grown on h-BN dielectric layers via vdW epitaxy. In addition, high carrier mobility comparable to free-standing single-crystal counterparts is achieved by forming interfacial electrical contacts with graphene electrodes.

Structural and Electrical Investigation of C 60 –Graphene Vertical Heterostructures

Graphene, with its unique electronic and structural qualities, has become an important playground for studying adsorption and assembly of various materials including organic molecules. Moreover, organic/graphene vertical structures assembled by van der Waals interaction have potential for multifunctional device applications. Here, we investigate structural and electrical properties of vertical heterostructures composed of C60 thin film on graphene. The assembled film structure of C60 on graphene is investigated using transmission electron microscopy, which reveals a uniform morphology of C60 film on graphene with a grain size as large as 500 nm. The strong epitaxial relations between C60 crystal and graphene lattice directions are found, and van der Waals ab initio calculations support the observed phenomena. Moreover, using C60-graphene heterostructures, we fabricate vertical graphene transistors incorporating n-type organic semiconducting materials with an on/off ratio above 3 × 10(3). Our work demonstrates that graphene can serve as an excellent substrate for assembly of molecules, and attained organic/graphene heterostructures have great potential for electronics applications.

Development of functionalised multiwalled carbon nanotube/polyaniline composites for electrical applications

Combining intrinsically conducting polymers with carbon nanotubes (CNT) helps in creating composites with superior electrical and thermal characteristics. These composites are capable of replacing metals and semiconductors as they possess unique combination of electrical conductivity, flexibility, stretchability, softness and bio-compatibility. Their potential for use in various organic devices such as super capacitors, printable conductors, optoelectronic devices, sensors, actuators, electrochemical devices, electromagnetic interference shielding, field effect transistors, LEDs, thermoelectrics etc. makes them excellent substitutes for present day semiconductors.However, many of these potential applications have not been fully exploited because of various open–ended challenges. Composites meant for use in organic devices require highly stable conductivity for the longevity of the devices. CNT when incorporated at specific proportions, and with special methods contributes quite positively to this end.The increasing demand for energy and depleting fossil fuel reserves has broadened the scope for research into alternative energy sources. A unique and efficient method for harnessing energy is thermoelectric energy conversion method. Here, heat is converted directly into electricity using a class of materials known as thermoelectric materials. Though polymers have low electrical conductivity and thermo power, their low thermal conductivity favours use as a thermoelectric material. The thermally disconnected, but electrically connected carrier pathways in CNT/Polymer composites can satisfy the so-called “phonon-glass/electron-crystal” property required for thermoelectric materials. Strain sensing is commonly used for monitoring in engineering, medicine, space or ocean research. Polymeric composites are ideal candidates for the manufacture of strain sensors. Conducting elastomeric composites containing CNT are widely used for this application. These CNT/Polymer composites offer resistance change over a large strain range due to the low Young‟s modulus and higher elasticity. They are also capable of covering surfaces with arbitrary curvatures.Due to the high operating frequency and bandwidth of electronic equipments electromagnetic interference (EMI) has attained the tag of an „environmental pollutant‟, affecting other electronic devices as well as living organisms. Among the EMI shielding materials, polymer composites based on carbon nanotubes show great promise. High strength and stiffness, extremely high aspect ratio, and good electrical conductivity of CNT make it a filler of choice for shielding applications. A method for better dispersion, orientation and connectivity of the CNT in polymer matrix is required to enhance conductivity and EMI shielding. This thesis presents a detailed study on the synthesis of functionalised multiwalled carbon nanotube/polyaniline composites and their application in electronic devices. The major areas focused include DC conductivity retention at high temperature, thermoelectric, strain sensing and electromagnetic interference shielding properties, thermogravimetric, dynamic mechanical and tensile analysis in addition to structural and morphological studies.

Lennar Technology: The Connected Consumer Has Arrived in Multifamily

As multifamily homebuilders progress into the 21st century, they have looked to integrate electronics and technology to simplify and enhance their businesses. The use of programs like Yardi and MRI for both property management and accounting have become the standard. Like Moore’s Law – the observation that the number of transistors in a dense integrated circuit will double approximately every two years – the use of technology in multifamily properties must equal both the pace and demand of present and future tenants.

Développement de procédés technologiques pour une intégration 3D monolithique de dispositifs nanoélectroniques sur CMOS

Résumé : Le transistor monoélectronique (SET) est un dispositif nanoélectronique très attractif à cause de son ultra-basse consommation d’énergie et sa forte densité d’intégration, mais il n’a pas les capacités suffisantes pour pouvoir remplacer complètement la technologie CMOS. Cependant, la combinaison de la technologie SET avec celle du CMOS est une voie intéressante puisqu’elle permet de profiter des forces de chacune, afin d’obtenir des circuits avec des fonctionnalités additionnelles et uniques. Cette thèse porte sur l’intégration 3D monolithique de nanodispositifs dans le back-end-of-line (BEOL) d’une puce CMOS. Cette approche permet d’obtenir des circuits hybrides et de donner une valeur ajoutée aux puces CMOS actuelles sans altérer le procédé de fabrication du niveau des transistors MOS. L’étude se base sur le procédé nanodamascène classique développé à l’UdeS qui a permis la fabrication de dispositifs nanoélectroniques sur un substrat de SiO2. Ce document présente les travaux réalisés sur l’optimisation du procédé de fabrication nanodamascène, afin de le rendre compatible avec le BEOL de circuits CMOS. Des procédés de gravure plasma adaptés à la fabrication de nanostructures métalliques et diélectriques sont ainsi développés. Le nouveau procédé nanodamascène inverse a permis de fabriquer des jonctions MIM et des SET métalliques sur une couche de SiO2. Les caractérisations électriques de MIM et de SET formés avec des jonctions TiN/Al2O3 ont permis de démontrer la présence de pièges dans les jonctions et la fonctionnalité d’un SET à basse température (1,5 K). Le transfert de ce procédé sur CMOS et le procédé d’interconnexions verticales sont aussi développés par la suite. Finalement, un circuit 3D composé d’un nanofil de titane connecté verticalement à un transistor MOS est réalisé et caractérisé avec succès. Les résultats obtenus lors de cette thèse permettent de valider la possibilité de co-intégrer verticalement des dispositifs nanoélectroniques avec une technologie CMOS, en utilisant un procédé de fabrication compatible.

Développement de la polymérisation par (hétéro)arylation directe pour l’électronique organique

L’électronique organique suscite un intérêt grandissant en recherche grâce aux nouvelles possibilités qu’elle offre pour faciliter l’intégration de dispositifs électroniques dans nos vies. Grâce à elle, il est possible d’envisager des produits légers, flexibles et peu coûteux à produire. Les classes majeures de dispositifs étudiées sont les cellules photovoltaïques organiques (CPO) et les transistors organiques à effet de champ (TOEC). Dans les dernières années, une attention particulière a été portée sur les méthodes de polymérisation des matériaux organiques entrant dans la fabrication de ces dispositifs. La polymérisation par (hétéro)arylation directe (PHAD) catalysée au Pd offre une synthèse sans dérivé organométallique utilisant simplement un lien C-H aromatique, ce qui facilite la purification, diminue le nombre d’étapes et rend possible la production de matériaux à plus faible coût. De plus, la PHAD permet la préparation de matériaux qui était difficile, voire impossible, à obtenir auparavant. Cependant, l’inconvénient majeur de la PHAD reste sa limitation à certaines classes de polymères possédant des monomères ayant des positions bloquées favorisant qu’une seule paire de liaisons C-H. Dans le cadre de ces travaux de doctorat, l’objectif général est d’étudier la polymérisation par PHAD afin d’accéder à des classes de monomères qui n’étaient pas envisageables auparavant et à étendre l’application de cet outil dans le domaine des polymères conjugués. Plus spécifiquement, nous avons étudié l’utilisation de groupements protecteurs et partants sur des unités de benzodithiophènes et de bithiophène-silylés. Suivant ces résultats, nos travaux ont porté sur la polymérisation de dérivés de bithiophènes avec des bromo(aryle)s, une classe de polymères fréquemment utilisée en électronique organique mais qui était jugée impossible à polymériser par PHAD auparavant. Cette étude a montré l’importance de contrôler la PHAD afin d’obtenir le polymère souhaité. Finalement, nous avons étudié l’effet du système catalytique sur le taux de β−ramifications lors de la synthèse de polymères à base de thiophènes. Dans cette dernière étude, nous avons démontré l’importance d’utiliser des outils de caractérisation adéquats afin de confirmer la qualité des polymères obtenus.

STRAINING ENGINEERING OF GRAPHENE AND GRAPHENE-BASED NANOSTRUCTURES

Graphene has emerged as an extraordinary material with its capability to accommodate an array of remarkable electronic, mechanical and chemical properties. Extra-large surface-to-volume ratio renders graphene a highly flexible morphology, giving rise to intriguing observations such as ripples, wrinkles and folds as well as the potential to transform into other novel carbon nanostructures. Ultra-thin, mechanically tough, electrically conductive graphene films promise to enable a wealth of possible applications ranging from hydrogen storage scaffolds, electronic transistors, to bottom-up material designs. Enthusiasm for graphene-based applications aside, there are still significant challenges to their realization, largely due to the difficulty of precisely controlling the graphene properties. Controlling the graphene morphology over large areas is crucial in enabling future graphene-based applications and material design. This dissertation aims to shed lights on potential mechanisms to actively manipulate the graphene morphology and properties and therefore enable the material design principle that delivers desirable mechanical and electronic functionalities of graphene and its derivatives.

Electrical and optical studies on carbon nanotube arrays

Single-walled carbon nanotubes (SWNTs) have been studied as a prominent class of high performance electronic materials for next generation electronics. Their geometry dependent electronic structure, ballistic transport and low power dissipation due to quasi one dimensional transport, and their capability of carrying high current densities are some of the main reasons for the optimistic expectations on SWNTs. However, device applications of individual SWNTs have been hindered by uncontrolled variations in characteristics and lack of scalable methods to integrate SWNTs into electronic devices. One relatively new direction in SWNT electronics, which avoids these issues, is using arrays of SWNTs, where the ensemble average may provide uniformity from device to device, and this new breed of electronic material can be integrated into electronic devices in a scalable fashion. This dissertation describes (1) methods for characterization of SWNT arrays, (2) how the electrical transport in these two-dimensional arrays depend on length scales and spatial anisotropy, (3) the interaction of aligned SWNTs with the underlying substrate, and (4) methods for scalable integration of SWNT arrays into electronic devices. The electrical characterization of SWNT arrays have been realized by polymer electrolyte-gated SWNT thin film transistors (TFTs). Polymer electrolyte-gating addresses many technical difficulties inherent to electrical characterization by gating through oxide-dielectrics. Having shown polymer electrolyte-gating can be successfully applied on SWNT arrays, we have studied the length scaling dependence of electrical transport in SWNT arrays. Ultrathin films formed by sub-monolayer surface coverage of SWNT arrays are very interesting systems in terms of the physics of two-dimensional electronic transport. We have observed that they behave qualitatively different than the classical conducting films, which obey the Ohm’s law. The resistance of an ultrathin film of SWNT arrays is indeed non-linear with the length of the film, across which the transport occurs. More interestingly, a transition between conducting and insulating states is observed at a critical surface coverage, which is called percolation limit. The surface coverage of conducting SWNTs can be manipulated by turning on and off the semiconductors in the SWNT array, leading to the operation principle of SWNT TFTs. The percolation limit depends also on the length and the spatial orientation of SWNTs. We have also observed that the percolation limit increases abruptly for aligned arrays of SWNTs, which are grown on single crystal quartz substrates. In this dissertation, we also compare our experimental results with a two-dimensional stick network model, which gives a good qualitative picture of the electrical transport in SWNT arrays in terms of surface coverage, length scaling, and spatial orientation, and briefly discuss the validity of this model. However, the electronic properties of SWNT arrays are not only determined by geometrical arguments. The contact resistances at the nanotube-nanotube and nanotube-electrode (bulk metal) interfaces, and interactions with the local chemical groups and the underlying substrates are among other issues related to the electronic transport in SWNT arrays. Different aspects of these factors have been studied in detail by many groups. In fact, I have also included a brief discussion about electron injection onto semiconducting SWNTs by polymer dopants. On the other hand, we have compared the substrate-SWNT interactions for isotropic (in two dimensions) arrays of SWNTs grown on Si/SiO2 substrates and horizontally (on substrate) aligned arrays of SWNTs grown on single crystal quartz substrates. The anisotropic interactions associated with the quartz lattice between quartz and SWNTs that allow near perfect horizontal alignment on substrate along a particular crystallographic direction is examined by Raman spectroscopy, and shown to lead to uniaxial compressive strain in as-grown SWNTs on single crystal quartz. This is the first experimental demonstration of the hard-to-achieve uniaxial compression of SWNTs. Temperature dependence of Raman G-band spectra along the length of individual nanotubes reveals that the compressive strain is non-uniform and can be larger than 1% locally at room temperature. Effects of device fabrication steps on the non-uniform strain are also examined and implications on electrical performance are discussed. Based on our findings, there are discussions about device performances and designs included in this dissertation. The channel length dependences of device mobilities and on/off ratios are included for SWNT TFTs. Time response of polymer-electrolyte gated SWNT TFTs has been measured to be ~300 Hz, and a proof-of-concept logic inverter has been fabricated by using polymer electrolyte gated SWNT TFTs for macroelectronic applications. Finally, I dedicated a chapter on scalable device designs based on aligned arrays of SWNTs, including a design for SWNT memory devices.

Growth and application of planar III-V semiconductor nanowires grown with MOCVD

The semiconductor nanowire has been widely studied over the past decade and identified as a promising nanotechnology building block with application in photonics and electronics. The flexible bottom-up approach to nanowire growth allows for straightforward fabrication of complex 1D nanostructures with interesting optical, electrical, and mechanical properties. III-V nanowires in particular are useful because of their direct bandgap, high carrier mobility, and ability to form heterojunctions and have been used to make devices such as light-emitting diodes, lasers, and field-effect transistors. However, crystal defects are widely reported for III-V nanowires when grown in the common out-of-plane <111>B direction. Furthermore, commercialization of nanowires has been limited by the difficulty of assembling nanowires with predetermined position and alignment on a wafer-scale. In this thesis, planar III-V nanowires are introduced as a low-defect and integratable nanotechnology building block grown with metalorganic chemical vapor deposition. Planar GaAs nanowires grown with gold seed particles self-align along the <110> direction on the (001) GaAs substrate. Transmission electron microscopy reveals that planar GaAs nanowires are nearly free of crystal defects and grow laterally and epitaxially on the substrate surface. The nanowire morphology is shown to be primarily controlled through growth temperature and an ideal growth window of 470 +\- 10 °C is identified for planar GaAs nanowires. Extension of the planar growth mode to other materials is demonstrated through growth of planar InAs nanowires. Using a sacrificial layer, the transfer of planar GaAs nanowires onto silicon substrates with control over the alignment and position is presented. A metal-semiconductor field-effect transistor fabricated with a planar GaAs nanowire shows bulk-like low-field electron transport characteristics with high mobility. The aligned planar geometry and excellent material quality of planar III-V nanowires may lead to highly integrated III-V nanophotonics and nanoelectronics.

Carbon nanotube films for flexible electronics

Discovering scalable routes to fabricate large scale electronic devices on flexible substrates has been the goal of the newly emerging field of flexible macroelectronics. Thin film transistors (TFTs) have been fabricated on flexible substrates by using organic small-molecule and polymer-based materials, or thin layers of crystalline inorganic semiconductors. Recently, films of carbon nanotubes have been proposed as electronic materials with superior electrical performance due to exceptional electrical and mechanical properties of single-walled carbon nanotubes (SWCNTs). In this thesis, some aspects of recent research efforts on integrating arrays of carbon nanotubes into macroelectronic devices are described. Carbon nanotube films have two major uses for flexible macroelectronics. The first approach uses carbon nanotube thin films as active semiconducting materials in the channel of flexible TFTs. Even though, high-performance carbon nanotube thin film transistors have been realized, the electronic non-homogeneity of the as-grown carbon nanotubes in the film limits the device performance for some applications. In this thesis, the application of electrochemical functionalization on carbon nanotube films to improve the electronic homogeneity of the film is described. The effect of the crystal quartz substrates on the growth rate of carbon nanotubes, and whether this can be used to sort out as-grown carbon nanotubes by electronic type is also discussed. Finally, I argue that high density carbon nanotube films can also be used as highly conducting stretchable interconnects on mechanically flexible electronic circuits. The sheet resistance and the nature of the buckling of carbon nanotube films on flexible substrates are discussed.

Design and development of distributed feedback transistor lasers

The transistor laser is a unique three-port device that operates simultaneously as a transistor and a laser. With quantum wells incorporated in the base regions of heterojunction bipolar transistors, the transistor laser possesses advantageous characteristics of fast base spontaneous carrier lifetime, high differential optical gain, and electrical-optical characteristics for direct “read-out” of its optical properties. These devices have demonstrated many useful features such as high-speed optical transmission without the limitations of resonance, non-linear mixing, frequency multiplication, negative resistance, and photon-assisted switching. To date, all of these devices operate as multi-mode lasers without any type of wavelength selection or stabilizing mechanisms. Stable single-mode distributed feedback diode laser sources are important in many applications including spectroscopy, as pump sources for amplifiers and solid-state lasers, for use in coherent communication systems, and now as TLs potentially for integrated optoelectronics. The subject of this work is to expand the future applications of the transistor laser by demonstrating the theoretical background, process development and device design necessary to achieve singlelongitudinal- mode operation in a three-port transistor laser. A third-order distributed feedback surface grating is fabricated in the top emitter AlGaAs confining layers using soft photocurable nanoimprint lithography. The device produces continuous wave laser operation with a peak wavelength of 959.75 nm and threshold current of 13 mA operating at -70 °C. For devices with cleaved ends a side-mode suppression ratio greater than 25 dB has been achieved.

Spatial and temporal measurements using polyoxometalate, enzymatic and biofilm layers on a CMOS 0.35 μm 64 X 64-pixel I.S.F.E.T. array sensor

This thesis presents the achievements and scientific work conducted using a previously designed and fabricated 64 x 64-pixel ion camera with the use of a 0.35 μm CMOS technology. We used an array of Ion Sensitive Field Effect Transistors (ISFETs) to monitor and measure chemical and biochemical reactions in real time. The area of our observation was a 4.2 x 4.3 mm silicon chip while the actual ISFET array covered an area of 715.8 x 715.8 μm consisting of 4096 ISFET pixels in total with a 1 μm separation space among them. The ion sensitive layer, the locus where all reactions took place was a silicon nitride layer, the final top layer of the austriamicrosystems 0.35 μm CMOS technology used. Our final measurements presented an average sensitivity of 30 mV/pH. With the addition of extra layers we were able to monitor a 65 mV voltage difference during our experiments with glucose and hexokinase, whereas a difference of 85 mV was detected for a similar glucose reaction mentioned in literature, and a 55 mV voltage difference while performing photosynthesis experiments with a biofilm made from cyanobacteria, whereas a voltage difference of 33.7 mV was detected as presented in literature for a similar cyanobacterial species using voltamemtric methods for detection. To monitor our experiments PXIe-6358 measurement cards were used and measurements were controlled by LabVIEW software. The chip was packaged and encapsulated using a PGA-100 chip carrier and a two-component commercial epoxy. Printed circuit board (PCB) has also been previously designed to provide interface between the chip and the measurement cards.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.

The development of planar high-K/III-V p-channel MOSFETs for post-silicon CMOS

Conventional Si complementary-metal-oxide-semiconductor (CMOS) scaling is fast approaching its limits. The extension of the logic device roadmap for future enhancements in transistor performance requires non-Si materials and new device architectures. III-V materials, due to their superior electron transport properties, are well poised to replace Si as the channel material beyond the 10nm technology node to mitigate the performance loss of Si transistors from further reductions in supply voltage to minimise power dissipation in logic circuits. However several key challenges, including a high quality dielectric/III-V gate stack, a low-resistance source/drain (S/D) technology, heterointegration onto a Si platform and a viable III-V p-metal-oxide-semiconductor field-effect-transistor (MOSFET), need to be addressed before III-Vs can be employed in CMOS. This Thesis specifically addressed the development and demonstration of planar III-V p-MOSFETs, to complement the n-MOSFET, thereby enabling an all III-V CMOS technology to be realised. This work explored the application of InGaAs and InGaSb material systems as the channel, in conjunction with Al2O3/metal gate stacks, for p-MOSFET development based on the buried-channel flatband device architecture. The body of work undertaken comprised material development, process module development and integration into a robust fabrication flow for the demonstration of p-channel devices. The parameter space in the design of the device layer structure, based around the III-V channel/barrier material options of In_x≥0.53Ga_1-xAs/In_0.52Al_0.48As and In_x≥0.1Ga_1-xSb/AlSb, was systematically examined to improve hole channel transport. A mobility of 433 cm²/Vs, the highest room temperature hole mobility of any InGaAs quantum-well channel reported to date, was obtained for the In_0.85Ga_0.15As (2.1% strain) structure. S/D ohmic contacts were developed based on thermally annealed Au/Zn/Au metallisation and validated using transmission line model test structures. The effects of metallisation thickness, diffusion barriers and de-oxidation conditions were examined. Contacts to InGaSb-channel structures were found to be sensitive to de-oxidation conditions. A fabrication process, based on a lithographically-aligned double ohmic patterning approach, was realised for deep submicron gate-to-source/drain gap (L_side) scaling to minimise the access resistance, thereby mitigating the effects of parasitic S/D series resistance on transistor performance. The developed process yielded gaps as small as 20nm. For high-k integration on GaSb, ex-situ ammonium sulphide ((NH₄)₂S) treatments, in the range 1%-22%, for 10min at 295K were systematically explored for improving the electrical properties of the Al₂O₃/GaSb interface. Electrical and physical characterisation indicated the 1% treatment to be most effective with interface trap densities in the range of 4 - 10×10¹²cm^-2eV^-1 in the lower half of the bandgap. An extended study, comprising additional immersion times at each sulphide concentration, was further undertaken to determine the surface roughness and the etching nature of the treatments on GaSb. A number of p-MOSFETs based on III-V-channels with the most promising hole transport and integration of the developed process modules were successfully demonstrated in this work. Although the non-inverted InGaAs-channel devices showed good current modulation and switch-off characteristics, several aspects of performance were non-ideal; depletion-mode operation, modest drive current (I_d,sat=1.14mA/mm), double peaked transconductance (g_m=1.06mS/mm), high subthreshold swing (SS=301mV/dec) and high on-resistance (R_on=845kΩ.μm). Despite demonstrating substantial improvement in the on-state metrics of I_d,sat (11×), g_m (5.5×) and R_on (5.6×), inverted devices did not switch-off. Scaling gate-to-source/drain gap (L_side) from 1μm down to 70nm improved I_d,sat (72.4mA/mm) by a factor of 3.6 and gm (25.8mS/mm) by a factor of 4.1 in inverted InGaAs-channel devices. Well-controlled current modulation and good saturation behaviour was observed for InGaSb-channel devices. In the on-state In_0.3Ga_0.7Sb-channel (I_d,sat=49.4mA/mm, g_m=12.3mS/mm, R_on=31.7kΩ.μm) and In_0.4Ga_0.6Sb-channel (I_d,sat=38mA/mm, g_m=11.9mS/mm, R_on=73.5kΩ.μm) devices outperformed the InGaAs-channel devices. However the devices could not be switched off. These findings indicate that III-V p-MOSFETs based on InGaSb as opposed to InGaAs channels are more suited as the p-channel option for post-Si CMOS.

Architectural-Physical Co-Design of 3D CPUs with Micro-Fluidic Cooling

The performance, energy efficiency and cost improvements due to traditional technology scaling have begun to slow down and present diminishing returns. Underlying reasons for this trend include fundamental physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a growing mismatch between transistors and interconnects regarding size, speed and power. Continued Moore's Law scaling will not come from technology scaling alone, and must involve improvements to design tools and development of new disruptive technologies such as 3D integration. 3D integration presents potential improvements to interconnect power and delay by translating the routing problem into a third dimension, and facilitates transistor density scaling independent of technology node. Furthermore, 3D IC technology opens up a new architectural design space of heterogeneously-integrated high-bandwidth CPUs. Vertical integration promises to provide the CPU architectures of the future by integrating high performance processors with on-chip high-bandwidth memory systems and highly connected network-on-chip structures. Such techniques can overcome the well-known CPU performance bottlenecks referred to as memory and communication wall. However the promising improvements to performance and energy efficiency offered by 3D CPUs does not come without cost, both in the financial investments to develop the technology, and the increased complexity of design. Two main limitations to 3D IC technology have been heat removal and TSV reliability. Transistor stacking creates increases in power density, current density and thermal resistance in air cooled packages. Furthermore the technology introduces vertical through silicon vias (TSVs) that create new points of failure in the chip and require development of new BEOL technologies. Although these issues can be controlled to some extent using thermal-reliability aware physical and architectural 3D design techniques, high performance embedded cooling schemes, such as micro-fluidic (MF) cooling, are fundamentally necessary to unlock the true potential of 3D ICs. A new paradigm is being put forth which integrates the computational, electrical, physical, thermal and reliability views of a system. The unification of these diverse aspects of integrated circuits is called Co-Design. Independent design and optimization of each aspect leads to sub-optimal designs due to a lack of understanding of cross-domain interactions and their impacts on the feasibility region of the architectural design space. Co-Design enables optimization across layers with a multi-domain view and thus unlocks new high-performance and energy efficient configurations. Although the co-design paradigm is becoming increasingly necessary in all fields of IC design, it is even more critical in 3D ICs where, as we show, the inter-layer coupling and higher degree of connectivity between components exacerbates the interdependence between architectural parameters, physical design parameters and the multitude of metrics of interest to the designer (i.e. power, performance, temperature and reliability). In this dissertation we present a framework for multi-domain co-simulation and co-optimization of 3D CPU architectures with both air and MF cooling solutions. Finally we propose an approach for design space exploration and modeling within the new Co-Design paradigm, and discuss the possible avenues for improvement of this work in the future.