Parenting advantage in the MNC: An embeddedness perspective on the value added by headquarters

What determines the value an MNC’s headquarters adds to its own affiliates? In this paper, we shed light on this question by linking the embeddedness view of the multinational corporation to the literature on parenting advantage. We test our hypotheses on an original dataset of 124 manufacturing subsidiaries located in Europe. Our results indicate that the external embeddedness of the MNC is an antecedent to headquarters’ value creation. We find that headquarters’ investments into their own relationships with the subsidiaries’ contexts are positively related to the value added by headquarters. Furthermore, this relationship is stronger when the subsidiary itself is strongly embedded. We discuss implications for the MNC literature, embeddedness research, and the literature on parenting and headquarters’ roles. Copyright © 2013 John Wiley & Sons, Ltd.

Defining a Research Agenda in Value Driven Design: Questions That Need to be Asked

Value driven design is an innovative design process that utilizes the optimization of a system level value function to determine the best possible design. This contrasts with more traditional systems engineering techniques, which rely on satisfying requirements to determine the design solution. While ‘design for value’ is intuitively acceptable, the transformation of value driven design concepts into practical tools and methods for its application is challenging. This, coupled with the growing popularity of value-centric design philosophies, has led to a proposed research agenda in value driven design. This research agenda asks fundamental questions about the design philosophy and attempts to identify areas of significant challenge. The research agenda is meant to stimulate discussion in the field, as well as prompt research that will lead to the development of tools and methodologies that will facilitate the application of value driven design and further the state of the art.

An Analytical Study of Surplus Value using a Value Driven Design Methodology

People are now becoming more environmentally aware and as a consequence of this, industries such as the aviation industry are striving to design more environmentally friendly products. To achieve this, the current design methodologies must be modified to ensure these issues are considered from product conception through to disposal. This paper discusses the environmental problems in relation to the aviation industry and highlights some logic for making the change from the traditional Systems Engineering approach to the recent design paradigm known as Value Driven Design. Preliminary studies have been undertaken to aid in the understanding of this methodology and the existing surplus value objective function. The main results from the work demonstrate that surplus value works well bringing disparate issues such as manufacture and green taxes together to aid decision making. Further, to date studies on surplus value have used simple sensitivity analysis, but deeper consideration shows non-linear interactions between some of the variables and further work will be needed to fully account for complex issues such as environmental impact and taxes.

Valved Dataflow For FPGA Memory Hierarchy Synthesis

For modern FPGA, implementation of memory intensive processing applications such as high end image and video processing systems necessitates manual design of complex multilevel memory hierarchies incorporating off-chip DDR and onchip BRAM and LUT RAM. In fact, automated synthesis of multi-level memory hierarchies is an open problem facing high level synthesis technologies for FPGA devices. In this paper we describe the first automated solution to this problem.
By exploiting a novel dataflow application modelling dialect, known as Valved Dataflow, we show for the first time how, not only can such architectures be automatically derived, but also that the resulting implementations support real-time processing for current image processing application standards such as H.264. We demonstrate the viability of this approach by reporting the performance and cost of hierarchies automatically generated for Motion Estimation, Matrix Multiplication and Sobel Edge Detection applications on Virtex-5 FPGA.