Small angle scattering characterisation of micellar systems and templated architectures

The work described in this thesis reports the structural changes induced on micelles under a variety of conditions. The micelles of a liquid crystal film and dilute solutions of micelles were subjected to high pressure CO2 and selected hydrocarbon environments. Using small angle neutron scattering (SANS) techniques the spacing between liquid crystal micelles was measured in-situ. The liquid crystals studied were templated from different surfactants with varying structural characteristics. Micelles of a dilute surfactant solution were also subjected to elevated pressures of varying gas atmospheres. Detailed modelling of the in-situ SANS experiments revealed information of the size and shape of the micelles at a number of different pressures. Also reported in this thesis is the characterisation of mesoporous materials in the confined channels of larger porous materials. Periodic mesoporous organosilicas (PMOs) were synthesised within the channels of anodic alumina membranes (AAM) under different conditions, including drying rates and precursor concentrations. In-situ small angle x-ray scattering (SAXS) and transmission electron microscopy (TEM) was used to determine the pore morphology of the PMO within the AAM channels. PMO materials were also used as templates in the deposition of gold nanoparticles and subsequently used in the synthesis of germanium nanostructures. Polymer thin films were also employed as templates for the directed deposition of gold nanoparticles which were again used as seeds for the production of germanium nanostructures. A supercritical CO2 (sc-CO2) technique was successfully used during the production of the germanium nanostructures.

Low power predictable memory and processing architectures

Great demand in power optimized devices shows promising economic potential and draws lots of attention in industry and research area. Due to the continuously shrinking CMOS process, not only dynamic power but also static power has emerged as a big concern in power reduction. Other than power optimization, average-case power estimation is quite significant for power budget allocation but also challenging in terms of time and effort. In this thesis, we will introduce a methodology to support modular quantitative analysis in order to estimate average power of circuits, on the basis of two concepts named Random Bag Preserving and Linear Compositionality. It can shorten simulation time and sustain high accuracy, resulting in increasing the feasibility of power estimation of big systems. For power saving, firstly, we take advantages of the low power characteristic of adiabatic logic and asynchronous logic to achieve ultra-low dynamic and static power. We will propose two memory cells, which could run in adiabatic and non-adiabatic mode. About 90% dynamic power can be saved in adiabatic mode when compared to other up-to-date designs. About 90% leakage power is saved. Secondly, a novel logic, named Asynchronous Charge Sharing Logic (ACSL), will be introduced. The realization of completion detection is simplified considerably. Not just the power reduction improvement, ACSL brings another promising feature in average power estimation called data-independency where this characteristic would make power estimation effortless and be meaningful for modular quantitative average case analysis. Finally, a new asynchronous Arithmetic Logic Unit (ALU) with a ripple carry adder implemented using the logically reversible/bidirectional characteristic exhibiting ultra-low power dissipation with sub-threshold region operating point will be presented. The proposed adder is able to operate multi-functionally.

Secure architectures for pairing based public key cryptography

Along with the growing demand for cryptosystems in systems ranging from large servers to mobile devices, suitable cryptogrophic protocols for use under certain constraints are becoming more and more important. Constraints such as calculation time, area, efficiency and security, must be considered by the designer. Elliptic curves, since their introduction to public key cryptography in 1985 have challenged established public key and signature generation schemes such as RSA, offering more security per bit. Amongst Elliptic curve based systems, pairing based cryptographies are thoroughly researched and can be used in many public key protocols such as identity based schemes. For hardware implementions of pairing based protocols, all components which calculate operations over Elliptic curves can be considered. Designers of the pairing algorithms must choose calculation blocks and arrange the basic operations carefully so that the implementation can meet the constraints of time and hardware resource area. This thesis deals with different hardware architectures to accelerate the pairing based cryptosystems in the field of characteristic two. Using different top-level architectures the hardware efficiency of operations that run at different times is first considered in this thesis. Security is another important aspect of pairing based cryptography to be considered in practically Side Channel Analysis (SCA) attacks. The naively implemented hardware accelerators for pairing based cryptographies can be vulnerable when taking the physical analysis attacks into consideration. This thesis considered the weaknesses in pairing based public key cryptography and addresses the particular calculations in the systems that are insecure. In this case, countermeasures should be applied to protect the weak link of the implementation to improve and perfect the pairing based algorithms. Some important rules that the designers must obey to improve the security of the cryptosystems are proposed. According to these rules, three countermeasures that protect the pairing based cryptosystems against SCA attacks are applied. The implementations of the countermeasures are presented and their performances are investigated.

Energy storage: battery materials and architectures at the nanoscale

Enterprise Ireland (Project CFTD07325). European Commission (EU Framework 7 project Nanofunction, (Beyond CMOS Nanodevices for Adding Functionalities to CMOS) www.Nanofunction.eu EU ICT Network of Excellence, Grant No.257375)

Results of parallelisation of existing electromagnetic finite codes on some different parallel architectures

In this paper the results obtained from the parallelisation of some 3D industrial electromagnetic Finite Element codes within the ESPRIT Europort 2 project PARTEL are presented. The basic guidelines for the parallelisation procedure, based on the Bulk Synchronous Parallel approach, are presented and the encouraging results obtained in terms of speed-up on some selected test cases of practical design significance are outlined and discussed.