Design of high-efficiency diffraction gratings based on rigorous coupled-wave analysis for 800nm wavelength

We report on the design of a high diffraction efficiency multi-layer dielectric grating with wide incident angle and broad bandwidth for 800 nm. The optimized grating can achieve > 95% diffraction efficiency in the first order at an incident angle of 5 degrees from Littrow and a wavelength from 770nm to 830 nm, with peak diffraction efficiency of > 99.5% at 800 nm. The electric field distribution of the optimized multi-layer dielectric grating within the gratings ridge is 1.3 times enhancement of the incidence light, which presents potential high laser resistance ability. Because of its high-efficiency, wide incident, broad bandwidth and potential high resistance ability, the multi-layer dielectric grating should have practical application in Ti:sapphire laser systems.

Influence of SiO2 additional layers on the laser induced damage threshold of Ta2O5 films

A series or Ta2O5 films with different SiO2 additional layers including overcoat, undercoat and interlayer was prepared by electron beam evaporation under the same deposition process. Absorption of samples was measured using the surface thermal lensing (STL) technique. The electric field distributions of the samples were theoretical predicted using thin film design software (TFCalc). The laser induced damage threshold (LIDT) was assessed using an Nd:YAG laser operating at 1064 nm with a pulse length of 12 ns. It was found that SiO2 additional layers resulted in a slight increase of the absorption, whereas they exerted little influence on the microdefects. The electric field distribution among the samples was unchanged by adding an SiO2 overcoat and undercoat, yet was changed by adding an interlayer. SiO2 undercoat. The interlayer improved the LIDT greatly, whereas the SiO2 overcoat had little effect on the LIDT. (C) 2007 Elsevier Ltd. All rights reserved.

Analysis of SEB and SEGR in super-junction MOSFETs

The electric field distribution in the super junction power MOSFET is analyzed using analytical modeling and numerical simulations in this paper. The single-event burn-out (SEB) and single-event gate rupture (SEGR) phenomena in this device are studied in detail. It is demonstrated that the super junction device is much less sensitive to SEB and SEGR compared to the standard power MOSFET. The physical mechanism is explained.

Analytical model for the 3D-RESURF effect

This paper presents an analytical model for the determination of the basic breakdown properties of three-dimensional (3D)-RESURF/CoolMOS/super junction type structures. To account for the two-dimensional (2D) effect of the 3D-RESURF action, 2D models of the electric field distribution are developed. Based on these, expressions are derived for the breakdown voltage as a function of doping concentration and physical dimensions. In addition to cases where the drift regions are fully depleted, the model developed is also applicable to situations involving drift regions which are almost depleted. Accuracy of the analytical approach is verified by comparison with numerical results obtained from the MEDICI device simulator.

Low on-resistance SOI dual-trench-gate MOSFET

A low specific on-resistance (R-{{\rm on}, {\rm sp}}) integrable silicon-on-insulator (SOI) MOSFET is proposed, and its mechanism is investigated by simulation. The SOI MOSFET features double trenches and dual gates (DTDG SOI): an oxide trench in the drift region, a buried gate inset in the oxide trench, and another trench gate (TG) extended to a buried oxide layer. First, the dual gates form dual conduction channels, and the extended gate widens the vertical conduction area; both of which sharply reduce R-{{\rm on}, {\rm sp}}. Second, the oxide trench folds the drift region in the vertical direction, resulting in a reduced device pitch and R-{{\rm on}, {\rm sp}}. Third, the oxide trench causes multidirectional depletion. This not only enhances the reduced surface field effect and thus reshapes the electric field distribution but also increases the drift doping concentration, leading to a reduced R-{{\rm on}, {\rm sp}} and an improved breakdown voltage (BV). Compared with a conventional SOI lateral Double-diffused metal oxide semiconductor (LDMOS), the DTDG MOSFET increases BV from 39 to 92 V at the same cell pitch or decreases R-{{\rm on}, { \rm sp}} by 77% at the same BV by simulation. Finally, the TG extended synchronously acts as an isolation trench between the high/low-voltage regions in a high-voltage integrated circuit, saving the chip area and simplifying the isolation process. © 2006 IEEE.

Study of second generation, high-temperature superconducting coils: Determination of critical current

This paper presents the modeling of second generation (2 G) high-temperature superconducting (HTS) pancake coils using finite element method. The axial symmetric model can be used to calculate current and magnetic field distribution inside the coil. The anisotropic characteristics of 2 G tapes are included in the model by direct interpolation. The model is validated by comparing to experimental results. We use the model to study critical currents of 2 G coils and find that 100μV/m is too high a criterion to determine long-term operating current of the coils, because the innermost turns of a coil will, due to the effect of local magnetic field, reach their critical current much earlier than outer turns. Our modeling shows that an average voltage criterion of 20μV/m over the coil corresponds to the point at which the innermost turns' electric field exceeds 100μV/m. So 20μV/m is suggested to be the critical current criterion of the HTS coil. The influence of background field on the coil critical current is also studied in the paper. © 2012 American Institute of Physics.

200-V lateral superjunction LIGBT on partial SOI

This letter presents a novel lateral superjunction lateral insulated-gate bipolar transistor (LIGBT) in partial silicon-on-insulator (SOI) technology in 0.18-μm partial-SOI (PSOI) high-voltage (HV) process. For an n-type superjunction LIGBT, the p-layer in the superjunction drift region not only helps in achieving uniform electric field distribution but also contributes to the on-state current. The superjunction LIGBT successfully achieves a breakdown voltage (BV) of 210 V with an R dson of 765 mΩ ̇ mm 2. It exhibits half the value of specific on-state resistance R dson and three times higher saturation current (I dsat) for the same BV, compared to a comparable lateral superjunction laterally diffused metal-oxide-semiconductor fabricated in the same technology. It also performs well in higher temperature dc operation with 38.8% increase in R dson at 175°C, compared to the room temperature without any degradation in latch-up performance. To realize this device, it only requires one additional mask layer into X-FAB 0.18-μm PSOI HV process. © 2012 IEEE.

Experimental and numerical study of a YBCO pancake coil with a magnetic substrate

A finite element model for a YBCO pancake coil with a magnetic substrate is developed in this paper. An axial symmetrical H formulation and the E-J power law are used to construct the model, with the magnetic substrate considered by introducing an extra time-dependent term in the formula. A pancake coil is made and tested. The measurement of critical current and transport loss is compared to the model result, showing good consistency. The influence of magnetic substrate in the condition of AC and DC current is studied. The AC loss decreases without a magnetic substrate. It is observed that when the applied DC current approaches the critical current the coil turn loss profile changes completely in the presence of magnetic substrate due to the change of magnetic field distribution. © 2012 IOP Publishing Ltd.

The lateral superjunction PSOI LIGBT and LDMOSFET

This paper presents a comparison between the superjunction LIGBT and the LDMOSFET in partial silicon-on-insulator (PSOI) technology in 0.18μm PSOI HV process. The superjunction drift region helps in achieving uniform electric field distribution in both structures but also contributes to the on-state current in the LIGBT. The superjunction LIGBT successfully achieves breakdown voltage (BV) of 210V with Rdson of 765mΩ.mm2. It exhibits reduced specific on-state resistance Rdson and higher saturation current (Idsat) for the same BV compared to a compatible lateral superjunction LDMOS in the same technology. © 2012 IEEE.

Study by Hall probe mapping of the trapped flux modification produced by local heating in YBCO HTS bulks for different surface/volume ratios

The aim of this report is to compare the trapped field distribution under a local heating created at the sample edge for different sample morphologies. Hall probe mappings of the magnetic induction trapped in YBCO bulk samples maintained out of thermal equilibrium were performed on YBCO bulk single domains, YBCO single domains with regularly spaced hole arrays, and YBCO superconducting foams. The capability of heat draining was quantified by two criteria: the average induction decay and the size of the thermally affected zone caused by a local heating of the sample. Among the three investigated sample shapes, the drilled single domain displays a trapped induction which is weakly affected by the local heating while displaying a high trapped field. Finally, a simple numerical modelling of the heat flux spreading into a drilled sample is used to suggest some design rules about the hole configuration and their size. © 2005 IOP Publishing Ltd.

200V superjunction lateral IGBT fabricated on partial SOI

A 200V lateral insulated gate bipolar transistor (LIGBT) was successfully developed using lateral superjunction (SJ) in 0.18μm partial silicon on insulator (SOI) HV process. The results presented are based on extensive experimental measurements and numerical simulations. For an n-type lateral SJ LIGBT, the p layer in the SJ drift region helps in achieving uniform electric field distribution. Furthermore, the p-pillar contributes to the on-state current. Furthermore, the p-pillar contributes to sweep out holes during the turn-off process, thus leading to faster removal of plasma. To realize this device, one additional mask layer is required in the X-FAB 0.18μm partial SOI HV process. © 2013 IEEE.

Finite element beam propagation method for analysis of plasmonic waveguide

The basic idea of the finite element beam propagation method (FE-BPM) is described. It is applied to calculate the fundamental mode of a channel plasmonic polariton (CPP) waveguide to confirm its validity. Both the field distribution and the effective index of the, fundamental mode are given by the method. The convergence speed shows the advantage and stability of this method. Then a plasmonic waveguide with a dielectric strip deposited on a metal substrate is investigated, and the group velocity is negative for the fundamental mode of this kind of waveguide. The numerical result shows that the power flow direction is reverse to that of phase velocity.

Research on the influence of fabrication parameters on the performance of buried ion-exchanged glass waveguides using the variational method

The variational method is proposed to analyze the influence of the fabrication parameters on the performance of buried K+-Na+ ion-exchanged Er3+-Yb3+ ions co-doped glass waveguide. The unknown parameters of the Hermite-Gaussian functions as the trial field distribution are determined based on the scalar variational principle. It is demonstrated that the results calculated in this paper agree with those measured in the experiment. The mode dimensions, the effective refractive index, and the overlap factor as the functions of the fabrication parameters are investigated. These results of the variational analysis are useful for the design and optimization of Er3+-Yb3+ ions co-doped waveguides.

Design of quantum cascade microcavity lasers based on Q factor versus etching depth

The choice of the etching depth for semiconductor microcavities is a compromise between a high Q factor and a difficult technique in a practical fabricating process. In this paper, the influences of the etching depth on mode Q factors for mid-infrared quantum cascade microcylinder and microsquare lasers around 4.8 and 7.8 mu m are simulated by three-dimensional (3D) finite-difference time-domain (FDTD) techniques. For the microcylinder and the microsquare resonators, the mode Q factors of the whispering-gallery modes (WGMs) increase exponentially and linearly with the increase in the etching depth, respectively Furthermore, the mode Q factors of some higher order transverse WGMs may be larger than that of the fundamental transverse WGM in 3D microsquares. Based on the field distribution of the vertical multilayer slab waveguide and the mode Q factors versus the etching depth, the necessary etching depth is chosen at the position where the field amplitude is 1% of the peak value of the slab waveguide. In addition, the influences of sidewall roughness on the mode Q factors are simulated for microsquare resonators by 2D FDTD simulation. (C) 2009 Optical Society of America

A mini-staged multi-stacked quantum cascade laser for improved optical and thermal performance

In this paper, a mini-staged multi-stacked quantum cascade laser structure with a designed wavelength of 4.7 mu m is presented. By introducing five 0.5 mu m thick high thermal conductivity InP interbuffer layers, the 60-stages active region core of the quantum cascade laser is divided into six equal parts. Based on simulation, this kind of quantum cascade laser with a 10 mu m ridge width gives nearly circular two-dimensional far-field distribution (FWHM = 32.8 degrees x 29 degrees) and good beam quality parameters M-2 = 1.32 x 1.31 in the fast axis (growth direction) and the slow axis (lateral direction). Due to the enhancement of lateral heat extraction through the interbuffer layers, compared to the conventional structure, a decrease of about 5-6% for the maximum temperature in the active region core of the mini-staged multi-stacked quantum cascade laser with indium-surrounded and gold-electroplated packaging profiles is obtained at all possible dissipated electrical power levels.