Investigation on the intergranular corrosion resistance of the AISI 316L(N) stainless steel after long time creep testing at 600 degrees C

The effect of precipitation on the corrosion resistance of AISI 316L(N) stainless steel previously exposed to creep tests at 600 degrees C for periods of up to 10 years, has been studied. The corrosion resistance was investigated in 2 M H(2)SO(4)+0.5 M NaCl+0.01 M KSCN solution at 30 degrees C by electrochemical methods. The results showed that the susceptibility to intergranular corrosion was highly affected by aging at 600 degrees C and creep testing time. The intergranular corrosion resistance decreased by more than twenty times when the creep testing time increased from 7500 h to 85,000 h. The tendency to passivation decreased and less protective films were formed on the creep tested samples. All tested samples also showed susceptibility to pitting. Grain boundary M(23)C(6) carbides were not found after long-term exposure at 600 degrees C and the corrosion behavior of the creep tested samples was attributed to intermetallic phases (mainly sigma phase) precipitation. (C) 2007 Elsevier Inc. All rights reserved.

Low-frequency noise and static analysis of the impact of the TiN metal gate thicknesses on n- and p-channel MuGFETs

The impact of the titanium nitride (TIN) gate electrode thickness has been investigated in n and p channel SOI multiple gate field effect transistors (MuGFETs) through low frequency noise charge pumping and static measurements as well as capacitance-voltage curves The results suggest that a thicker TIN metal gate electrode gives rise to a higher EOT a lower mobility and a higher interface trap density The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TIN metal gate thickness and at higher V(GF) In addition it is demonstrated that post deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TIN gate electrode thickness where a continuous variation of EOT and an increase on the degradation of the interface quality are observed (C) 2010 Elsevier Ltd All rights reserved

Influence of the sidewall crystal orientation, HfSiO nitridation and TiN metal gate thickness on n-MuGFETs under analog operation

This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high-k post-nitridation. TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high-k material is subjected to a nitridation step indicated a degradation of the Early voltage (V(EA)) values which resulted in a lower voltage gain. The 45 degrees rotated devices have a smaller V(EA) than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V(EA) degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices. (C) 2011 Elsevier Ltd. All rights reserved.

Threshold voltages of SOI MuGFETs

The multiple-gate field-effect transistor (MuGFET) is a device with a gate folded on different sides of the channel region. They are one of the most promising technological solutions to create high-performance ultra-scaled SOI CMOS. In this work, the behavior of the threshold voltage in double-gate, triple-gate and quadruple-gate SOI transistors with different channel doping concentrations is studied through three-dimensional numerical simulation. The results indicated that for double-gate transistors, one or two threshold voltages can be observed, depending on the channel doping concentration. However, in triple-gate and quadruple-gate it is possible to observe up to four threshold voltages due to the corner effect and the different doping concentration between the top and bottom of the Fin. (C) 2008 Elsevier Ltd. All rights reserved.

Analog performance of standard and strained triple-gate silicon-on-insulator nFinFETs

This work shows a comparison between the analog performance of standard and strained Si n-type triple-gate FinFETs with high-K dielectrics and TiN gate material. Different channel lengths and fin widths are studied. It is demonstrated that both standard and strained FinFETs with short channel length and narrow fins have similar analog properties, whereas the increase of the channel length degrades the early voltage of the strained devices, consequently decreasing the device intrinsic voltage gain with respect to standard ones. Narrow strained FinFETs with long channel show a degradation of the Early voltage if compared to standard ones suggesting that strained devices are more subjected to the channel length modulation effect. (C) 2008 Elsevier Ltd. All rights reserved.

Improved generation lifetime model for the electrical characterization of single- and double-gate SOI nMOSFETs

This work proposes a refined technique for the extraction of the generation lifetime in single- and double-gate partially depleted SOI nMOSFETs. The model presented in this paper, based on the drain current switch-off transients, takes into account the influence of the laterally non-uniform channel doping, caused by the presence of the halo implanted region, and the amount of charge controlled by the drain and source junctions on the floating body effect when the channel length is reduced. The obtained results for single- gate (SG) devices are compared with two-dimensional numerical simulations and experimental data, extracted for devices fabricated in a 0.1 mu m SOI CMOS technology, showing excellent agreement. The improved model to determine the generation lifetime in double-gate (DG) devices beyond the considerations previously presented also consider the influence of the silicon layer thickness on the drain current transient. The extracted data through the improved model for DG devices were compared with measurements and two-dimensional numerical simulations of the SG devices also presenting a good adjustment with the channel length reduction and the same tendency with the silicon layer thickness variation.

Temperature influence on the gate-induced floating body effect parameters in fully depleted SOI nMOSFETs

The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a ""C"" shape of the threshold voltage corresponding with the second peak in the gm curve. (C) 2008 Elsevier Ltd. All rights reserved.

Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS

This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this represents the major non-linearity source in balanced structures. The 2-MOS structures with devices of different channel lengths (L) and fin widths (W(fin)) have been studied operating in the linear region as tunable resistors. The analysis was performed as a function of the gate voltage, aiming to verify the correlation between operation bias and HD3. The physical origins of the non-linearities have been investigated and are pointed out. Being a resistive circuit, the 2-MOS structure is generally projected for a targeted on-resistance, which has also been evaluated in terms of HD3. The impact of the application of biaxial strain has been studied for FinFETs of different dimensions. It has been noted that HD3 reduces with the increase of the gate bias for all the devices and this reduction is more pronounced both in narrower and in longer devices. Also, the presence of strain slightly diminishes the non-linearity at a similar bias. However, a drawback associated with the use of strain engineering consists in a significant reduction of the on-resistance with respect to unstrained devices. (C) 2011 Elsevier Ltd. All rights reserved.

Impact of SEG on uniaxially strained MuGFET performance

This work focuses on the impact of the source and drain Selective Epitaxial Growth (SEG) on the performance of uniaxially strained MuGFETs. With the channel length reduction, the normalized transconductance (gm.L./W) of unstressed MuGFETs decreases due to the series resistance and short channel effects (SCE), while the presence of uniaxial strain improves the gm. The competition between the series resistance (R(s)) and the uniaxial strain results in a normalized gm maximum point for a specific channel length. Since the SEG structure influences both R(s) and the strain in the channel, this work studies from room down to low temperature how these effects influence the performance of the triple-gate FETs. For lower temperatures, the strain-induced mobility enhancement increases and leads to a shift in the maximum point towards shorter channel lengths for devices without SEG. This shift is not observed for devices with SEG where the strain level is much lower. At 150 K the gm behavior of short channel strained devices with SEG is similar to the non SEC ones due to the better gm temperature enhancement for devices without SEG caused by the strain. For lower temperatures SEG structure is not useful anymore. (C) 2011 Elsevier Ltd. All rights reserved.

Flatness-based control of a single qubit gate

This work considers the open-loop control problem of steering a two-level quantum system from any initial to any final condition. The model of this system evolves on the state space X = SU(2), having two inputs that correspond to the complex amplitude of a resonant laser field. A symmetry preserving flat output is constructed using a fully geometric construction and quaternion computations. Simulation results of this flatness-based open-loop control are provided.

Cr3C2-NiCr and WC-Ni thermal spray coatings as alternatives to hard chromium for erosion-corrosion resistance

Cr3C2-NiCr and WC-Ni coatings are widely used for wear applications at high and room temperature, respectively. Due to the high corrosion resistance of NiCr binder, Cr3C2-NiCr coatings are also used in corrosive environments. The application of WC-Ni coatings in corrosive media is 14 not recommended due to the poor corrosion resistance of the (pure Ni) metallic matrix. It is well known that the addition of Cr to the metallic binder improves the corrosion properties. Erosion-corrosion performance of thermal spray coatings is widely influenced by ceramic phase composition, the size of ceramic particles and also the composition of the metallic binder. In the present work, two types of HVOF thermal spray coatings (Cr3C2-NiCr and WC-Ni) obtained with different spray conditions were studied and compared with conventional micro-cracked hard chromium coatings. Both as-sprayed and polished samples were tested under two erosion-corrosion conditions with different erosivity. Tungsten carbide coatings showed better performance under the most erosive condition, while chromium carbide coatings were superior under less erosive conditions. Some of the tungsten carbide coatings and hard chromium showed similar erosion-corrosion behaviour under more and less erosive conditions. The erosion-corrosion and electrochemical results showed that surface polishing improved the erosion-corrosion properties of the thermally sprayed coatings. The corrosion behaviour of the different coatings has been compared using Electrochemical Impedance Spectroscopy (EIS) and polarization curves. Total material loss due to erosion-corrosion was determined by weight loss measurements. An estimation of the corrosion contribution to the total weight loss was also given. (c) 2007 Elsevier B.V. All rights reserved.

Junctionless Multiple-Gate Transistors for Analog Applications

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width W(fin) and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage V(EA) and larger intrinsic voltage gain A(V) than IM devices of similar dimensions. In addition, V(EA) and A(V) are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors.

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-a round (GAA) devices operating in saturation region for analog applications. The study has been performed through device characterization and two-dimensional process and device simulations. The overall study has been done on the total and third order HDs. When applied in the saturation regime as an amplifier, the GC outperforms conventional GAA transistors presenting simultaneously higher transconductance, lower drain output conductance and more than 15 dB improved linearity. The influence of channel length reduction on the H D is also analyzed. Although slight linearity degradation is observed in both the conventional and the GC devices when reducing the channel length, the HD presented by the GC transistor is significantly lower than the one showed by conventional device for any Studied channel length. This allows AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level. (C) 2008 Elsevier Ltd. All rights reserved.

Novel sources of witches` broom resistance (causal agent Moniliophthora perniciosa) from natural populations of Theobroma cacao from the Brazilian Amazon

Witches` broom is a severe disease of Theobroma cacao L. (cacao), caused by the basidiomycete Moniliophthora perniciosa. The use of resistant cultivars is the ultimate method of control, but there are limited sources of resistance. Further, resistance from the most widely used source (`Scavina 6`) has been overcome after a few years of deployment. New sources of resistance have been intensively searched for in the Amazon basin. Here, we evaluated for witches` broom resistance, cacao accessions from various natural cacao populations originally collected in the Brazilian Amazon. Resistance of 43 families was evaluated under nursery and/or field conditions by artificial or natural infection, respectively, based on disease incidence. Screening for resistance by artificial inoculation under nursery conditions appeared to be efficient in identifying these novel resistance sources, confirmed by natural field evaluation over a nine-year period. The increase in natural field infection of `Scavina 6` was clearly demonstrated. Among the evaluated families with the least witches` broom incidence, there were accessions originally collected from distinct river basins, including the Jamari river (`CAB 0371`; `CAB 0388`; `CAB 0392`; and `CAB 0410`); Acre (`CAB 0169`); Javari (`CAB 0352`); Solimes (`CAB 0270`); and from the Purus river basin, the two most outstanding resistant accessions, `CAB 0208` and `CAB 0214`. The large genetic diversity found in cacao populations occurring at river basins from Acre and Amazonas states, Brazil, increased the chance that the selected resistant accessions would be genetically more dissimilar, and represent distinct sources of resistance to M. perniciosa from `Scavina 6`.

Progeny evaluation for resistance to Phaeosphaeria leaf spot in tropical maize

Maize breeding programmes in Brazil and elsewhere seek reliable methods to identify genotypes resistant to Phaeosphaeria leaf spot. The area under the disease progress curve (AUDPC) is an accurate method to evaluate the severity of foliar diseases. However, at least three data points are required to calculate the AUDPC, which is unfeasible when there are thousands of genotypes to be assessed. The aim of this work was to estimate the heritability of disease resistance, evaluate disease severity at different times using a nine-point scale in comparison to the AUDPC, and establish the most suitable phenological period for disease assessment. A repeated experiment was conducted in a 11 x 11 lattice experimental design with three replications. Disease assessments were carried out at flowering, 15 and 30 days post-anthesis for the parental lines DS95, DAS21, the F1 generation and 118 F2:3 progenies. Then, the AUDPC was obtained and results compared with the single-point evaluations used to calculate it. Individual and joint analyses of variance were conducted to obtain heritabiliy estimates. The assessments performed after the flowering stage gave higher estimates of heritability and correlation with AUDPC. We concluded that one assessment between the 15th and 30th day after flowering could provide enough information to distinguish maize genotypes for their resistance to Phaeosphaeria leaf spot under tropical conditions.