974 resultados para Station-based processing


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Matrix algorithms are important in many types of applications including image and signal processing. A close examination of the algorithms used in these, and related, applications reveals that many of the fundamental actions involve matrix algorithms such as matrix multiplication. This paper presents an investigation into the design and implementation of different matrix algorithms such as matrix operations, matrix transforms and matrix decompositions using a novel custom coprocessor system for MATrix algorithms based on Reconfigurable Computing (RCMAT). The proposed RCMAT architectures are scalable, modular and require less area and time complexity with reduced latency when compared with existing structures.

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This article reflects on the changing environment through the passage of time and how certain technologies for a creative proposal allow the preservation and transmission of a significant part of that ephemeral heritage for future generations. The general purpose of this particular project is aimed to achieve the sound synthesis of a specific and representative cityscape as the old train station in Cuenca –located in the heart of the city– that could be preserved and reproduced as an unique document of a present time, ascertainable in the future: a memory that interpret sound as a time capsule. This soundscape was made to mark the arrival of the high speed train in 2010 to a brand new station in the outskirts of the city. Therefore, the goal of this research was focused on achieving a synthetic document that provided a sound memory capable of reflecting the significant social, cultural and logistical features, of what was until then the only railway communication symbol in the city of Cuenca from 1883 to the first decade of the 21st century.

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To enable reliable data transfer in next generation Multiple-Input Multiple-Output (MIMO) communication systems, terminals must be able to react to fluctuating channel conditions by having flexible modulation schemes and antenna configurations. This creates a challenging real-time implementation problem: to provide the high performance required of cutting edge MIMO standards, such as 802.11n, with the flexibility for this behavioural variability. FPGA softcore processors offer a solution to this problem, and in this paper we show how heterogeneous SISD/SIMD/MIMD architectures can enable programmable multicore architectures on FPGA with similar performance and cost as traditional dedicated circuit-based architectures. When applied to a 4×4 16-QAM Fixed-Complexity Sphere Decoder (FSD) detector we present the first soft-processor based solution for real-time 802.11n MIMO.

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The paper presents IPPro which is a high performance, scalable soft-core processor targeted for image processing applications. It has been based on the Xilinx DSP48E1 architecture using the ZYNQ Field Programmable Gate Array and is a scalar 16-bit RISC processor that operates at 526MHz, giving 526MIPS of performance. Each IPPro core uses 1 DSP48, 1 Block RAM and 330 Kintex-7 slice-registers, thus making the processor as compact as possible whilst maintaining flexibility and programmability. A key aspect of the approach is in reducing the application design time and implementation effort by using multiple IPPro processors in a SIMD mode. For different applications, this allows us to exploit different levels of parallelism and mapping for the specified processing architecture with the supported instruction set. In this context, a Traffic Sign Recognition (TSR) algorithm has been prototyped on a Zedboard with the colour and morphology operations accelerated using multiple IPPros. Simulation and experimental results demonstrate that the processing platform is able to achieve a speedup of 15 to 33 times for colour filtering and morphology operations respectively, with a reduced design effort and time.

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The Field Programmable Gate Array (FPGA) implementation of the commonly used Histogram of Oriented Gradients (HOG) algorithm is explored. The HOG algorithm is employed to extract features for object detection. A key focus has been to explore the use of a new FPGA-based processor which has been targeted at image processing. The paper gives details of the mapping and scheduling factors that influence the performance and the stages that were undertaken to allow the algorithm to be deployed on FPGA hardware, whilst taking into account the specific IPPro architecture features. We show that multi-core IPPro performance can exceed that of against state-of-the-art FPGA designs by up to 3.2 times with reduced design and implementation effort and increased flexibility all on a low cost, Zynq programmable system.

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This paper employs a unique decentralised cooperative control method to realise a formation-based collision avoidance strategy for a group of autonomous vehicles. In this approach, the vehicles' role in the formation and their alert and danger areas are first defined, and the formation-based intra-group and external collision avoidance methods are then proposed to translate the collision avoidance problem into the formation stability problem. The extension–decomposition–aggregation formation control method is next employed to stabilise the original and modified formations, whilst manoeuvring, and subsequently solve their collision avoidance problem indirectly. Simulation study verifies the feasibility and effectiveness of the intra-group and external collision avoidance strategy. It is demonstrated that both formation control and collision avoidance problems can be simultaneously solved if the stability of the expanded formation including external obstacles can be satisfied.