Expression pattern of four storage xyloglucan mobilization-related genes during seedling development of the rain forest tree Hymenaea courbaril L.

During seedling establishment, cotyledons of the rain forest tree Hymenaea courbaril mobilize storage cell wall xyloglucan to sustain growth. The polysaccharide is degraded and its products are transported to growing sink tissues. Auxin from the shoot controls the level of xyloglucan hydrolytic enzymes. It is not yet known how important the expression of these genes is for the control of storage xyloglucan degradation. In this work, partial cDNAs of the genes xyloglucan transglycosylase hydrolase (HcXTH1) and beta-galactosidase (HcBGAL1), both related to xyloglucan degradation, and two other genes related to sucrose metabolism [alkaline invertase (HcAlkIN1) and sucrose synthase (HcSUS1)], were isolated. The partial sequences were characterized by comparison with sequences available in the literature, and phylogenetic trees were assembled. Gene expression was evaluated at intervals of 6 h during 24 h in cotyledons, hypocotyl, roots, and leaves, using 45-d-old plantlets. HcXTH1 and HcBGAL1 were correlated to xyloglucan degradation and responded to auxin and light, being down-regulated when transport of auxin was prevented by N-1-naphthylphthalamic acid (NPA) and stimulated by constant light. Genes related to sucrose metabolism, HcAlkIN1 and HcSUS1, responded to inhibition of auxin transport in consonance with storage mobilization in the cotyledons. A model is proposed suggesting that auxin and light are involved in the control of the expression of genes related to storage xyloglucan mobilization in seedlings of H. courbaril. It is concluded that gene expression plays a role in the control of the intercommunication system of the source-sink relationship during seeding growth, favouring its establishment in the shaded environment of the rain forest understorey.

Benzyladenine sprays and senescent flowers removal on postproduction performance of Potted zinnia 'Profusion cherry'

'Profusion Cherry' is a dwarf zinnia with prospect for pot use in Brazil. The success of flowering potted plants depends on its performance during transport and on the period of time that it performs well indoors. Benzyladenine application may retard leaf and flower senescence, increasing postproduction longevity and quality. Senescent flowers removal by consumers, to give a fresh appearance to home flowering potted plant, could influence source-sink relationship and postproduction. This study evaluated the effect of benzyladenine and senescent flowers removal on postproduction performance of 'Profusion Cherry', and observed the senescence symptoms. When plants, produced in greenhouse at São Paulo State, Brazil, had 4 to 5 open flowers, they were sprayed to runoff a single time (20ml/pot) with benzyladenine (0.4, 0.6, 0.8 or 1.0 mmol) and placed into plastic trays, without sleeve. The experimental design was a randomized blocks with 6 treatments (control, four benzyladenine concentrations and senescent flowers removal), 4 replications (2 pots per experimental unit), totalising 12 potted plants in each plastic tray (block). To simulate highway transport, plants remained for 4 days in a dark chamber, at 20.0 °C without irrigation. To include vibration, each plastic tray, was placed in an incubator shaker for 3hr a day, at 60 rpm, 25°C and darkness. After simulated transport, plants remained indoors (10h.day-1 with 18 μmol.m-2.s-1 PPF, 21.5 to 27.0°C and, 14 h.day-1 at darkness, 18.5 to 24.0°C) during 21 days. Plants performed well during simulated transport, and also indoors for two weeks. For most of evaluated parameters there was not significant effect of benzyladenine concentrations by Tukey's test. Senescent flowers removal did not delayed senescence or improved plants quality. The symptoms associated with the loss of decorative life were ray florets color fading and wilting, without abscission of flowers or petals.

The use of the carbon-13 in the partitioning of photosynthate in vegetative and reproductive twigs of 'Sweet' passion fruit

This study's objective is to evaluate the photosynthates partitioning and source-sink relationships, in vegetative and reproductive twigs of sweet passion fruit, using the carbon-13, stable isotope of carbon. The leaves of vegetative and reproductive twigs were placed in a sealed chamber and 13CO 2 were injected for 30 minutes. After six hours, the different organs of the twig were collected and immersed in liquid nitrogen (-196°C). All plant samples were oven-dried, powdered and combusted in an elemental analyzer. The results showed that the methodology was efficient to evaluate the partitioning of photosynthates. In the vegetative twigs, the new open leaves, the closed leaves and growth meristem were the principal sink for the source leaves enriched with 13CO 2. In the reproductive twigs with only flowers buds, the source-sink relationship was changed and the flowers buds turn to be the principal sink and the growing leaves were secondary sinks. The presence of young fruits changed again the source-sink relationship of the twig, and they were the principal sinks. The apical leaves, with 60% of final leaf area were also a sink for photosynthates.

Deposição e caracterização de filmes finos de GaAs e 'Al IND. 2''O IND. 3' para potencial utilizado em transistores

Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)

Investigação de propriedades de filmes finos de Sn'O IND. 2' e 'Al IND. 2''O IND. 3' para aplicação em dispositivos

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Desempenho agronômico de híbridos de milho em diferentes arranjos populacionais em Jaboticabal-SP

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Uso do carbono-13 como marcador na partição de fotoassimilados em maracujazeiro doce (Passiflora alata Dryander)

Pós-graduação em Agronomia (Horticultura) - FCA

Study of silicon-on-insulator multiple-gate MOS structures including band-gap engineering and self heating effects

The progresses of electron devices integration have proceeded for more than 40 years following the well–known Moore’s law, which states that the transistors density on chip doubles every 24 months. This trend has been possible due to the downsizing of the MOSFET dimensions (scaling); however, new issues and new challenges are arising, and the conventional ”bulk” architecture is becoming inadequate in order to face them. In order to overcome the limitations related to conventional structures, the researchers community is preparing different solutions, that need to be assessed. Possible solutions currently under scrutiny are represented by: • devices incorporating materials with properties different from those of silicon, for the channel and the source/drain regions; • new architectures as Silicon–On–Insulator (SOI) transistors: the body thickness of Ultra-Thin-Body SOI devices is a new design parameter, and it permits to keep under control Short–Channel–Effects without adopting high doping level in the channel. Among the solutions proposed in order to overcome the difficulties related to scaling, we can highlight heterojunctions at the channel edge, obtained by adopting for the source/drain regions materials with band–gap different from that of the channel material. This solution allows to increase the injection velocity of the particles travelling from the source into the channel, and therefore increase the performance of the transistor in terms of provided drain current. The first part of this thesis work addresses the use of heterojunctions in SOI transistors: chapter 3 outlines the basics of the heterojunctions theory and the adoption of such approach in older technologies as the heterojunction–bipolar–transistors; moreover the modifications introduced in the Monte Carlo code in order to simulate conduction band discontinuities are described, and the simulations performed on unidimensional simplified structures in order to validate them as well. Chapter 4 presents the results obtained from the Monte Carlo simulations performed on double–gate SOI transistors featuring conduction band offsets between the source and drain regions and the channel. In particular, attention has been focused on the drain current and to internal quantities as inversion charge, potential energy and carrier velocities. Both graded and abrupt discontinuities have been considered. The scaling of devices dimensions and the adoption of innovative architectures have consequences on the power dissipation as well. In SOI technologies the channel is thermally insulated from the underlying substrate by a SiO2 buried–oxide layer; this SiO2 layer features a thermal conductivity that is two orders of magnitude lower than the silicon one, and it impedes the dissipation of the heat generated in the active region. Moreover, the thermal conductivity of thin semiconductor films is much lower than that of silicon bulk, due to phonon confinement and boundary scattering. All these aspects cause severe self–heating effects, that detrimentally impact the carrier mobility and therefore the saturation drive current for high–performance transistors; as a consequence, thermal device design is becoming a fundamental part of integrated circuit engineering. The second part of this thesis discusses the problem of self–heating in SOI transistors. Chapter 5 describes the causes of heat generation and dissipation in SOI devices, and it provides a brief overview on the methods that have been proposed in order to model these phenomena. In order to understand how this problem impacts the performance of different SOI architectures, three–dimensional electro–thermal simulations have been applied to the analysis of SHE in planar single and double–gate SOI transistors as well as FinFET, featuring the same isothermal electrical characteristics. In chapter 6 the same simulation approach is extensively employed to study the impact of SHE on the performance of a FinFET representative of the high–performance transistor of the 45 nm technology node. Its effects on the ON–current, the maximum temperatures reached inside the device and the thermal resistance associated to the device itself, as well as the dependence of SHE on the main geometrical parameters have been analyzed. Furthermore, the consequences on self–heating of technological solutions such as raised S/D extensions regions or reduction of fin height are explored as well. Finally, conclusions are drawn in chapter 7.

Studio di transistor elettrochimici e loro applicazioni

In questa tesi, utilizzando le particolari proprietà del polimero conduttivo poli(3,4-etilenediossitiofene) drogato con polistirene sulfonato , o PEDOT:PSS, sono stati realizzati dei transistor elettrochimici organici (OECTs), in cui il gate e canale source-drain sono stati realizzati depositando su substrato di vetro film sottili di questo polimero. I dispositivi realizzati sono stati caratterizzati, per comprenderne meglio le funzionalità e le proprietà per possibili applicazioni future, in particolare come sensori di glucosio. Il PEDOT:PSS è uno dei materiali più studiati per applicazioni della bioelettronica in virtù della sua grande stabilità chimica e termica, della reversibilità del suo processo di drogaggio, della grande conducibilità e delle sue proprietà elettrochimiche, nonché della sua attività in un vasto range di pH. Vengono trattate nell’elaborato anche le tecniche di deposizione di questo polimero per la creazione di film sottili, necessari per le varie applicazioni nell’ambito della bioelettronica organica, la quale si propone di unire la biologia e l’elettronica in un mutuale scambio di informazioni e segnali. Questa interazione si sta verificando soprattutto nel campo sanitario, come si può evincere dagli esempi riportati nella trattazione. Si conclude la parte teorica con una descrizione degli OECTs: viene spiegata la loro struttura, la capacità di connettere conducibilità ionica ed elettronica e il loro funzionamento, inserendo anche un confronto con i FET (“Field Effect Transistor”), per agevolare la comprensione dei meccanismi presenti in questi strumenti. Per la parte sperimentale si presenta invece una descrizione dettagliata dei procedimenti, degli strumenti e degli accorgimenti usati nel fabbricare i transistor sui quali si è lavorato in laboratorio, riportando anche una piccola esposizione sulle principali misure effettuate: curve caratterische I–V, transcaratteristiche e misure di corrente nel tempo sono le principali acquisizioni fatte per studiare i dispositivi. E’ stata studiata la diversa risposta degli OECTs al variare della concentrazione di PBS in soluzione, mostrando un generale rallentamento dei processi e una diminuzione della capacità di modificare la corrente source-drain al calare della concentrazione. In seguito, è stato effettuato un confronto tra transistor appena fatti e gli stessi analizzati dopo un mese, osservando una riduzione della corrente e quindi della conducibilità, seppur senza una modifica qualitativa delle curve caratteristiche (che mantengono il loro andamento). Per quanto riguarda la possibilità di usare questi dispositivi come sensori di glucosio, si introduce uno studio preliminare sulla risposta di un transistor, il cui gate è stato funzionalizzato con ferrocene, alla presenza di glucosio e glucosio ossidasi, un enzima necessario al trasferimento di elettroni, nella soluzione elettrolitica, seppur con qualche difficoltà, per via della mancanza di informazioni sui parametri da utilizzare e il range in cui compiere le misure (tuttora oggetto di ricerca).

Development of room temperature operating single electron transistor using FIB etching and deposition technology

The single-electron transistor (SET) is one of the best candidates for future nano electronic circuits because of its ultralow power consumption, small size and unique functionality. SET devices operate on the principle of Coulomb blockade, which is more prominent at dimensions of a few nano meters. Typically, the SET device consists of two capacitively coupled ultra-small tunnel junctions with a nano island between them. In order to observe the Coulomb blockade effects in a SET device the charging energy of the device has to be greater that the thermal energy. This condition limits the operation of most of the existing SET devices to cryogenic temperatures. Room temperature operation of SET devices requires sub-10nm nano-islands due to the inverse dependence of charging energy on the radius of the conducting nano-island. Fabrication of sub-10nm structures using lithography processes is still a technological challenge. In the present investigation, Focused Ion Beam based etch and deposition technology is used to fabricate single electron transistors devices operating at room temperature. The SET device incorporates an array of tungsten nano-islands with an average diameter of 8nm. The fabricated devices are characterized at room temperature and clear Coulomb blockade and Coulomb oscillations are observed. An improvement in the resolution limitation of the FIB etching process is demonstrated by optimizing the thickness of the active layer. SET devices with structural and topological variation are developed to explore their impact on the behavior of the device. The threshold voltage of the device was minimized to ~500mV by minimizing the source-drain gap of the device to 17nm. Vertical source and drain terminals are fabricated to realize single-dot based SET device. A unique process flow is developed to fabricate Si dot based SET devices for better gate controllability in the device characteristic. The device vi parameters of the fabricated devices are extracted by using a conductance model. Finally, characteristic of these devices are validated with the simulated data from theoretical modeling.

STOCHASTIC CHARGE TRANSPORT IN MULTI-ISLAND SINGLE-ELECTRON TUNNELING DEVICES

The physics of the operation of singe-electron tunneling devices (SEDs) and singe-electron tunneling transistors (SETs), especially of those with multiple nanometer-sized islands, has remained poorly understood in spite of some intensive experimental and theoretical research. This computational study examines the current-voltage (IV) characteristics of multi-island single-electron devices using a newly developed multi-island transport simulator (MITS) that is based on semi-classical tunneling theory and kinetic Monte Carlo simulation. The dependence of device characteristics on physical device parameters is explored, and the physical mechanisms that lead to the Coulomb blockade (CB) and Coulomb staircase (CS) characteristics are proposed. Simulations using MITS demonstrate that the overall IV characteristics in a device with a random distribution of islands are a result of a complex interplay among those factors that affect the tunneling rates that are fixed a priori (e.g. island sizes, island separations, temperature, gate bias, etc.), and the evolving charge state of the system, which changes as the source-drain bias (VSD) is changed. With increasing VSD, a multi-island device has to overcome multiple discrete energy barriers (up-steps) before it reaches the threshold voltage (Vth). Beyond Vth, current flow is rate-limited by slow junctions, which leads to the CS structures in the IV characteristic. Each step in the CS is characterized by a unique distribution of island charges with an associated distribution of tunneling probabilities. MITS simulation studies done on one-dimensional (1D) disordered chains show that longer chains are better suited for switching applications as Vth increases with increasing chain length. They are also able to retain CS structures at higher temperatures better than shorter chains. In sufficiently disordered 2D systems, we demonstrate that there may exist a dominant conducting path (DCP) for conduction, which makes the 2D device behave as a quasi-1D device. The existence of a DCP is sensitive to the device structure, but is robust with respect to changes in temperature, gate bias, and VSD. A side gate in 1D and 2D systems can effectively control Vth. We argue that devices with smaller island sizes and narrower junctions may be better suited for practical applications, especially at room temperature.

Geochemistry of DSDP Hole 83-504B minerals

Leg 83 of the Deep Sea Drilling Project has deepened Hole 504B to over 1 km into basement, 1350 m below the seafloor (BSF). The hole previously extended through 274.5 m of sediment and 561.5 m of pillow basalts altered at low temperature (< 100°C), to 836 m BSF. Leg 83 drilling penetrated an additional 10 m of pillows, a 209-m transition zone, and 295 m into a sheeted dike complex. Leg 83 basalts (836-1350 m BSF) generally contain superimposed greenschist and zeolite-facies mineral parageneses. Alteration of pillows and dikes from 836 to 898 m BSF occurred under reducing conditions at low water/rock ratios, and at temperatures probably greater than 100°C. Evolution of fluid composition resulted in the formation of (1) clay minerals, followed by (2) zeolites, anhydrite, and calcite. Alteration of basalts in the transition zone and dike sections (898-1350 m BSF) occurred in three basic stages, defined by the opening of fractures and the formation of characteristic secondary minerals. (1) Chlorite, actinolite, pyrite, albite, sphene, and minor quartz formed in veins and host basalts from partially reacted seawater (Mg-bearing, locally metal-and Si-enriched) at temperatures of at least 200-250°C. (2) Quartz, epidote, and sulfides formed in veins at temperatures of up to 380°C, from more evolved (Mg-depleted, metal-, Si-, and 18O-enriched) fluids. (3) The last stage is characterized by zeolite formation: (a) analcite and stilbite formed locally, possibly at temperatures less than 200°C followed by (b) formation of laumontite, heulàndite, scolecite, calcite, and prehnite from solutions depleted in Mg and enriched in Ca and 18O, at temperatures of up to 250°C. The presence of small amounts of anhydrite locally may be due to ingress of relatively unaltered seawater into the system during Stage 3. Alteration was controlled by the permeability of the crust and is characterized by generally incomplete recrystallization and replacement reactions among secondary minerals. Secondary mineralogy in the host basalts is strongly controlled by primary mineralogy. The alteration of Leg 83 basalts can be interpreted in terms of an evolving hydrothermal system, with (a) changes in solution composition because of reaction of seawater fluids with basalts at high temperatures; (b) variations in permeability caused by several stages of sealing and reopening of cracks; and (c) a general cooling of the system, caused either by the cooling of a magma chamber beneath the spreading center and/or the movement of the crust away from the heat source. The relationship of the high-temperature alteration in the transition zone and dike sections to the low-temperature alteration in the overlying pillow section remains uncertain.

Investigation of AlInN barrier ISFET structures with GaN capping for pH detection

In the last decade the interest in nitride-based sensors (gas, ions...) and bio-sensors is increased. In the case of ion sensitive FET (ISFET), gate voltages induced by ions adsorbed onto the gate region modulate the source-drain currents.

Effect of spatial inhomogeneity of charge carrier mobility on current-voltage characteristics in organic field-effect transistors

A semi-quantitative model is put forward elucidating the role of spatial inhomogeneity of charge carrier mobility in organic field-effect transistors. The model, based on electrostatic arguments, allows estimating the effective thickness of the conducting channel and its changes in function of source-drain and gate voltages. Local mobility gradients in the direction perpendicular to the insulator/semiconductor interface translate into voltage dependences of the average carrier mobility in the channel, resulting in positive or negative deviations of current-voltage characteristics from their expected shapes. The proposed effect supplements those described in the literature, i.e., density-dependent mobility of charge carriers, short-channel effects, and contribution of contact resistance.

A III-V channel field effect transistor for non-classical CMOS: process optimisation for improved gate stack function

This thesis describes a collection of studies into the electrical response of a III-V MOS stack comprising metal/GaGdO/GaAs layers as a function of fabrication process variables and the findings of those studies. As a result of this work, areas of improvement in the gate process module of a III-V heterostructure MOSFET were identified. Compared to traditional bulk silicon MOSFET design, one featuring a III-V channel heterostructure with a high-dielectric-constant oxide as the gate insulator provides numerous benefits, for example: the insulator can be made thicker for the same capacitance, the operating voltage can be made lower for the same current output, and improved output characteristics can be achieved without reducing the channel length further. It is known that transistors composed of III-V materials are most susceptible to damage induced by radiation and plasma processing. These devices utilise sub-10 nm gate dielectric films, which are prone to contamination, degradation and damage. Therefore, throughout the course of this work, process damage and contamination issues, as well as various techniques to mitigate or prevent those have been investigated through comparative studies of III-V MOS capacitors and transistors comprising various forms of metal gates, various thicknesses of GaGdO dielectric, and a number of GaAs-based semiconductor layer structures. Transistors which were fabricated before this work commenced, showed problems with threshold voltage control. Specifically, MOSFETs designed for normally-off (VTH > 0) operation exhibited below-zero threshold voltages. With the results obtained during this work, it was possible to gain an understanding of why the transistor threshold voltage shifts as the gate length decreases and of what pulls the threshold voltage downwards preventing normally-off device operation. Two main culprits for the negative VTH shift were found. The first was radiation damage induced by the gate metal deposition process, which can be prevented by slowing down the deposition rate. The second was the layer of gold added on top of platinum in the gate metal stack which reduces the effective work function of the whole gate due to its electronegativity properties. Since the device was designed for a platinum-only gate, this could explain the below zero VTH. This could be prevented either by using a platinum-only gate, or by matching the layer structure design and the actual gate metal used for the future devices. Post-metallisation thermal anneal was shown to mitigate both these effects. However, if post-metallisation annealing is used, care should be taken to ensure it is performed before the ohmic contacts are formed as the thermal treatment was shown to degrade the source/drain contacts. In addition, the programme of studies this thesis describes, also found that if the gate contact is deposited before the source/drain contacts, it causes a shift in threshold voltage towards negative values as the gate length decreases, because the ohmic contact anneal process affects the properties of the underlying material differently depending on whether it is covered with the gate metal or not. In terms of surface contamination; this work found that it causes device-to-device parameter variation, and a plasma clean is therefore essential. This work also demonstrated that the parasitic capacitances in the system, namely the contact periphery dependent gate-ohmic capacitance, plays a significant role in the total gate capacitance. This is true to such an extent that reducing the distance between the gate and the source/drain ohmic contacts in the device would help with shifting the threshold voltages closely towards the designed values. The findings made available by the collection of experiments performed for this work have two major applications. Firstly, these findings provide useful data in the study of the possible phenomena taking place inside the metal/GaGdO/GaAs layers and interfaces as the result of chemical processes applied to it. In addition, these findings allow recommendations as to how to best approach fabrication of devices utilising these layers.