967 resultados para Integrated circuit layout


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Electronic systems are a very good platform for sensing biological signals for fast point-of-care diagnostics or threat detection. One of the solutions is the lab-on-a-chip integrated circuit (IC), which is low cost and high reliability, offering the possibility for label-free detection. In recent years, similar integrated biosensors based on the conventional complementary metal oxide semiconductor (CMOS) technology have been reported. However, post-fabrication processes are essential for all classes of CMOS biochips, requiring biocompatible electrode deposition and circuit encapsulation. In this work, we present an amorphous silicon (a-Si) thin film transistor (TFT) array based sensing approach, which greatly simplifies the fabrication procedures and even decreases the cost of the biosensor. The device contains several identical sensor pixels with amplifiers to boost the sensitivity. Ring oscillator and logic circuits are also integrated to achieve different measurement methodologies, including electro-analytical methods such as amperometric and cyclic voltammetric modes. The system also supports different operational modes. For example, depending on the required detection arrangement, a sample droplet could be placed on the sensing pads or the device could be immersed into the sample solution for real time in-situ measurement. The entire system is designed and fabricated using a low temperature TFT process that is compatible to plastic substrates. No additional processing is required prior to biological measurement. A Cr/Au double layer is used for the biological-electronic interface. The success of the TFT-based system used in this work will open new avenues for flexible label-free or low-cost disposable biosensors. © 2013 Materials Research Society.

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This paper reports the development of solar-blind aluminum gallium nitride (AlGaN) 128x128 UV Focal Plane Arrays (FPAs). The back-illuminated hybrid FPA architecture consists of an 128x128 back-illuminated AlGaN PIN detector array that is bump-mounted to a matching 128x128 silicon CMOS readout integrated circuit (ROIC) chip. The 128x128 p-i-n photodiode arrays with cuton and cutoff wavelengths of 233 and 258 nm, with a sharp reduction in response to UVB (280-320 nm) light. Several examples of solar-blind images are provided. This solar-blind band FPA has much better application prospect.

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In this paper, a cellular neural network with depressing synapses for contrast-invariant pattern classification and synchrony detection is presented, starting from the impulse model of the single-electron tunneling junction. The results of the impulse model and the network are simulated using simulation program with integrated circuit emphasis (SPICE). It is demonstrated that depressing synapses should be an important candidate of robust systems since they exhibit a rapid depression of excitatory postsynaptic potentials for successive presynaptic spikes.

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In this work, we present the design of an integrated photonic-crystal polarization beam splitter (PC-PBS) and a low-loss photonic-crystal 60 waveguide bend. Firstly, the modal properties of the PC-PBS and the mechanism of the low-loss waveguide bend are investigated by the two-dimensional finite-difference time-domain (FDTD) method, and then the integration of the two devices is studied. It shows that, although the individual devices perform well separately, the performance of the integrated circuit is poor due to the multi-mode property of the PC-PBS. By introducing deformed airhole structures, a single-mode PC-PBS is proposed, which significantly enhance the performance of the circuit with the extinction ratios remaining above 20dB for both transverse-electric (TE) and transverse-magnetic (TM) polarizations. Both the specific result and the general idea of integration design are promising in the photonic crystal integrated circuits in the future. (C) 2009 Optical Society of America

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This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

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A semi-insulating GaAs single crystal ingot was grown in a recoverable satellite, within a specially designed pyrolytic boron nitride crucible, in a power-traveling furnace under microgravity. The characteristics of a compound semiconductor single crystal depends fundamentally on its stoichiometry, i.e. the ration of two types of atoms in the crystal. a practical technique for nondestructive and quantitative measuring stoichiometry in GaAs single crystal was used to analyze the space-grown GaAs single crystal. The distribution of stoichiometry in a GaAs wafer was measured for the first time. The electrical, optical and structural properties of the space-grown GaAs crystal were studied systematically, Device fabricating experiments prove that the quality of field effect transistors fabricated from direct ion-implantation in semi-insulating GaAs wafers has a close correlation with the crystal's stoichiometry. (C) 2000 Elsevier Science S.A. All rights reserved.

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GaAs single crystal has been grown in recoverable satellite. Hall measurements indicate that the GaAs shows semi-insulating behavior. The structural properties of the crystal have been improved obviously, and their uniformity has been improved as well. The stoichiometry and its distribution in space-grown GaAs are improved greatly compared with the GaAs single crystal grown terrestrially. The properties of integrated circuits made by direct ion-implantation on space-grown GaAs are better than those made on ground-grown materials. These results show that the stoichiometry in semi-insulating GaAs seriously affects the properties of related devices.

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FD SOI MOSFETs with MESA and Irradiated FD SOI MOSFETs with LOCOS isolation usually show the edge effect, that is, the leakage current called hump is generated in the subthreshold region. According to different reasons for generating the edge effect, rounded corner process and BTS structure are applied to improve device performance. The results indicate that the above two methods are effective to reduce the edge effect and qualified devices are fabricated successfully.

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The traditional monostable-bistable transition logic element (MOBILE) structure is usually composed of resonant tunneling diodes (RTD). This letter describes a new type MOBILE structure consisting of single-electron transistors (i.e. SET-MOBILE). The analytical model of single-electron transistors ( SET) has been considered three states (including an excited state) of the discrete quantum energy levels. The simulation results show negative differential conductance (NDC) characteristics in I-DS-V-DS curve. The SET-MOBILE utilizing NDC characteristics can successfully realize the basic logic functions as the RTD-MOBILE.

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The wetting layers (WL) in InAs/GaAs quantum-dot system have been studied by reflectance difference spectroscopy (RDS), in which two structures related to the heavy-hole (HH) and light-hole (LH) transitions in the WL have been observed. The evolution and segregation behaviors of WL during Stranski-Krastanow (SK) growth mode have been studied from the analysis of the WL-related optical transition energies. It has been found that the segregation coefficient of Indium atoms varies linearly with the InAs amount in WL. In addition, the effect of the growth temperature on the critical thickness for InAs island formation has also been studied. The critical thickness defined by the appearance of InAs dots, which is determined by AFM, shows a complex variation with the growth temperature. However, the critical thickness determined by RDS is almost constant in the range of 510-540 degrees C.

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High homoepitaxial growth of 4H-SiC has been performed in a home-made horizontal hot wall CVD reactor on n-type 4H-SiC 8 degrees off-oriented substrates in the size of 10 mm x 10 mm, using trichlorosilane (TCS) as silicon precursor source together with ethylene as carbon precursor source. Cross-section Scanning Electron Microscopy (SEM), Raman scattering spectroscopy and Atomic Force Microscopy (AFM) were used to determine the growth rate, structural property and surface morphology, respectively. The growth rate reached to 23 mu m/h and the optimal epilayer was obtained at 1600 degrees C with TCS flow rate of 12 seem in C/Si of 0.42, which has a good surface morphology with a low Rms of 0.64 nm in 10 mu mx10 mu m area.

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A detailed reaction-tran sport model was studied in a showerhead reactor for metal organic chemical vapor deposition of GaN film by using computational fluid dynamics simulation. It was found that flat flow lines without swirl are crucial to improve the uniformity of the film growth, and thin temperature gradient above the suscptor can increase the film deposition rate. By above-mentioned research, we can employ higher h (the distance from the susceptor to the inlet), P (operational pressure) and the rate of susceptor rotation to improve the film growth.

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When AlGaN is grown on GaN template, crack networks invariably generate when the thickness of the AlGaN layers over GaN exceeds the critical value. We used thin high temperature deposited AlN layer (HT-AlN) as the interlayer between GaN template and AlGaN epilayer which was very effective in eliminating the cracks in AlGaN epilayer. AlGaN layers with high Al mole fractions were also grown. Characterization showed that the crystalline quality of AlGaN epilayer was fairly good even when the At mole fraction was high.

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In this paper fabrication of high power light emitting diodes (LEDs) with combined transparent electrodes on both P-GaN and N-GaN have been demonstrated. Simulation and experimental results show that comparing with traditional metal N electrodes the efficacy of LEDs with transparent N electrode is increased by more than 10% and it is easier in process than the other techniques. Further more, combining the transparent electrodes with dielectric anti-reflection film, the extraction efficiency can be improved by 5%. At the same time, the transparent electrodes were protected by the dielectric film and the reliability of LEDs can be improved.

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AlGaN/AlN/GaN/InGaN/GaN double heterojunction high electron mobility transistors (DH-HEMTs) structures with improved buffer isolation have been investigated. The structures were grown by MOCVD on sapphire substrate. AFM result of this structure shows a good surface morphology with the root-mean-square roughness (RMS) of 0.196 nm for a scan area of 5 mu mx5 mu m. A mobility as high as 1950 cm(2)/Vs with the sheet carrier density of 9.89x10(12) cm(-2) was obtained, which was about 50% higher than other results of similar structures which have been reported. Average sheet resistance of 327 Omega/sq was achieved. The HEMTs device using the materials was fabricated, and a maximum drain current density of 718.5 mA/mm, an extrinsic transconductance of 248 mS/mm, a current gain cutoff frequency of 16 GHz and a maximum frequency of oscillation 35 GHz were achieved.