Detecção de faltas em sistemas de distribuição de energia elétrica usando dispositivos programáveis

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

Construção,modelagem e controle de um pêndulo invertido com CLP e software scada

Pós-graduação em Engenharia Elétrica - FEIS

LOGO2VHDL: modelos descritos em VHDL a partir da linguagem do LOGO!Soft Comfort da Siemens

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)

O uso do marketing B2B em pequenas e médias empresas: um estudo exploratório no setor de automação industrial do Vale do Paraíba paulista

Pós-graduação em Engenharia Mecânica - FEG

Controle de velocidade de um motor de indução trifásico usando técnicas de ajuste empírico para bancada de teste no laboratório de automação

This work aims to make the closed loop control of a three phase induction motor, through the integration of the following equipment: a frequency inverter, the actuator system; a programmable logic controller (PLC), the controller; an encoder, the velocity sensor, used as a feedback monitoring the control variable and the three-phase induction motor, the plant to be controlled. The control is performed using a Proportional - Integrative - Derivative (PID) approach. The PLC has a help instruction, which performs the auto adjustment of the controller, that instruction is used and confronted with other adjustment methods. There are several types of methods adjustments to the PID controllers, where the empirical methods are addressed in this work. The system is deployed at the Interface and Electro Electronic Control laboratory in the Universidade Estadual Paulista Júlio Mesquita Filho, Guaratinguetá, São Paulo, then, in the future, this work becomes an experiment to be conducted in the classroom, allowing undergraduate students to develop a greater affinity to the programs used by the PLC as well as studies of undergraduate and graduate works with the help of assembly made

Reversão sexual de tilápias gift criadas em hapas e submetidas a diferentes taxas de alimentação em alta frequência

Pós-graduação em Zootecnia - FMVZ

Synchronizing chaotic optically-programmable digital circuits

In this paper an approach to the synchronization of chaotic circuits has been reported. It is based on an optically programmable logic cell and the signals involved are fully digital. It is based on the reception of the same input signal on sender and receiver and from this approach, with a posterior correlation between both outputs, an identical chaotic output is obtained in both systems. No conversion from analog to digital signals is needed. The model here presented is based on a computer simulation.

Digital chaos analysis in optical logic structures

Digital chaotic behavior in an optically processing element is analyzed. It was obtained as the result of processing two fixed trains of bits. The process is performed with an optically programmable logic gate. Possible outputs, for some specific conditions of the circuit, are given. Digital chaotic behavior is obtained, by using a feedback configuration. Different ways to analyze a digital chaotic signal are presented.

Bit noise from an optical logic gate with laser diodes

Output bits from an optical logic cell present noise due to the type of technique used to obtain the Boolean functions of two input data bits. We have simulated the behavior of an optically programmable logic cell working with Fabry Perot-laser diodes of the same type employed in optical communications (1550nm) but working here as amplifiers. We will report in this paper a study of the bit noise generated from the optical non-linearity process allowing the Boolean function operation of two optical input data signals. Two types of optical logic cells will be analyzed. Firstly, a classical "on-off" behavior, with transmission operation of LD amplifier and, secondly, a more complicated configuration with two LD amplifiers, one working on transmission and the other one in reflection mode. This last configuration has nonlinear behavior emulating SEED-like properties. In both cases, depending on the value of a "1" input data signals to be processed, a different logic function can be obtained. Also a CW signal, known as control signal, may be apply to fix the type of logic function. The signal to noise ratio will be analyzed for different parameters, as wavelength signals and the hysteresis cycles regions associated to the device, in relation with the signals power level applied. With this study we will try to obtain a better understanding of the possible effects present on an optical logic gate with Laser Diodes.

Chaotic behaviour evaluation in optical logic gates with fractal concepts

A chaotic output was obtained previously by us, from an Optical Programmable Logic Cell when a feedback is added. Some time delay is given to the feedback in order to obtain the non-linear behavior. The working conditions of such a cell is obtained from a simple diagram with fractal properties. We analyze its properties as well as the influence of time delay on the characteristics of the working diagram. A further study of the chaotic obtained signal is presented.

Photonic switching architectures with logic cells

Possible switching architectures, with Optically Programmable Logic Cells - OPLCs - will be reported in this paper. These basic units, previously employed by us for some other applications mainly in optical computing, will be employed as main elements to switch optical communications signals. The main aspect to be considered is that because the nternal components of these cells have nonlinear behaviors, namely either pure bistable or SEED-like properties, several are the possibilities to be obtained. Moreover, because their properties are dependent, under certain condition, of the signal wavelength, they are apt to be employed in WDM systems and the final result will depend on the orresponding optical signal frequency. We will give special emphasis to the case where self-routing is achieved, namely to structures of the Batcher or Banyan type. In these cases, as it will be shown, there is the possibility to route any packet input to a certain direction according to its first bits. The number of possible outputs gives the number of bits needed to route signals. An advantage of this configuration is that a very versatile behavior may be allowed. The main one is the possibility to obtain configurations with different kinds of behavior, namely, Strictly Nonblocking, Wide-Sense Nonblocking or Rearrangeably Nonblocking as well as to eliminate switching conflicts at a certain intermediate stages.

Logic cells as basic structures to add/drop WDM information signals

Nowadays, in order to take advantage of fiber optic bandwidth, any optical communications system tends to be WDM. The way to extract a channel, characterized by a wavelength, from the optical fiber is to filter the specific wavelength. This gives the systems a low degree of freedom due to the fact of the static character of most of the employed devices. In this paper we will present a different way to extract channels from an optical fiber with WDM transmission. The employed method is based on an Optically Programmable Logic Cells (OPLC) previously published by us, for other applications as a chaotic generator or as basic element for optical computing. In this paper we will describe the configuration of the OPLC to be employed as a dropping device. It acts as a filter because it will extract the data carried by a concrete wavelength. It does depend, internally, on the wavelength. We will show how the intensity of the signal is able to select the chosen information from the line. It will be also demonstrated that a new idea of redundant information it is the way of selecting the concrete wavelength. As a matter of fact this idea is apparently the only way to use the OPLC as a dropping device. Moreover, based on these concepts, a similar way to route signals to different routes is reported. The basis is the use of photonic switching configurations, namely Batcher or Bayan structures, where the unit switching cells are the above indicated OPLCs.

A Dynamically Adaptable Bus Architecture for Trading-Off Among Performance, Consumption and Dependability in Cyber-Physical Systems

Cyber-Physical Systems need to handle increasingly complex tasks, which additionally, may have variable operating conditions over time. Therefore, dynamic resource management to adapt the system to different needs is required. In this paper, a new bus-based architecture, called ARTICo3, which by means of Dynamic Partial Reconfiguration, allows the replication of hardware tasks to support module redundancy, multi-thread operation or dual-rail solutions for enhanced side-channel attack protection is presented. A configuration-aware data transaction unit permits data dispatching to more than one module in parallel, or provide coalesced data dispatching among different units to maximize the advantages of burst transactions. The selection of a given configuration is application independent but context-aware, which may be achieved by the combination of a multi-thread model similar to the CUDA kernel model specification, combined with a dynamic thread/task/kernel scheduler. A multi-kernel application for face recognition is used as an application example to show one scenario of the ARTICo3 architecture.

Mitigação de falhas críticas em sistemas produtivos.

O cenário competitivo e globalizado em que as empresas estão inseridas, sobretudo a partir do século XXI, associados a ciclos de vida cada vez menores dos produtos, rigorosos requisitos de qualidade, além de políticas de preservação do meio ambiente, com redução de consumo energético e de recursos hídricos, somadas às exigências legais de melhores condições de trabalho, resultaram em uma quebra de paradigma nos processos produtivos até então concebidos. Como solução a este novo cenário produtivo pode-se citar o extenso uso da automação industrial, fato que resultou em sistemas cada vez mais complexos, tanto do ponto de vista estrutural, em função do elevado número de componentes, quanto da complexidade dos sistemas de controle. A previsibilidade de todos os estados possíveis do sistema torna-se praticamente impossível. Dentre os estados possíveis pode-se citar os estados de falha que, dependendo da severidade do efeito associado à sua ocorrência, podem resultar em sérios danos para o homem, o meio ambiente e às próprias instalações, caso não sejam corretamente diagnosticados e tratados. Fatos recentes de catástrofes relacionadas à sistemas produtivos revelam a necessidade de se implementar medidas para prevenir e para mitigar os efeitos da ocorrência de falhas, com o objetivo de se evitar a ocorrência de catástrofes. De acordo com especialistas, os Sistemas Instrumentados de Segurança SIS, referenciados em normas como a IEC 61508 e IEC 61511, são uma solução para este tipo de problema. Trabalhos publicados tratam de métodos para a implementação de camadas SIS de prevenção, porém com escassez de trabalhos para camadas SIS de mitigação. Em função do desconhecimento da dinâmica do sistema em estado de falha, técnicas tradicionais de modelagem tornam-se inviáveis. Neste caso, o uso de inteligência artificial, como por exemplo a lógica fuzzy, pode se tornar uma solução para o desenvolvimento do algoritmo de controle, associadas a ferramentas de edição, modelagem e geração dos códigos de controle. A proposta deste trabalho é apresentar uma sistemática para a implementação de um sistema de controle para a mitigação de falhas críticas em sistemas produtivos, com referência às normas IEC 61508/61511, com ação antecipativa à ocorrência de catástrofes.

Arquitetura híbrida com DSP e FPGA para implementação de controladores de filtros ativos de potência

The presence of non-linear loads at a point in the distribution system may deform voltage waveform due to the consumption of non-sinusoidal currents. The use of active power filters allows significant reduction of the harmonic content in the supply current. However, the processing of digital control structures for these filters may require high performance hardware, particularly for reference currents calculation. This work describes the development of hardware structures with high processing capability for application in active power filters. In this sense, it considers an architecture that allows parallel processing using programmable logic devices. The developed structure uses a hybrid model using a DSP and an FPGA. The DSP is used for the acquisition of current and voltage signals, calculation of fundamental current related controllers and PWM generation. The FPGA is used for intensive signal processing, such as the harmonic compensators. In this way, from the experimental analysis, significant reductions of the processing time are achieved when compared to traditional approaches using only DSP. The experimental results validate the designed structure and these results are compared with other ones from architectures reported in the literature.