Multi-μ: an Ada 95 based architecture for fault tolerance support of real-time systems

This paper presents an architecture (Multi-μ) being implemented to study and develop software based fault tolerant mechanisms for Real-Time Systems, using the Ada language (Ada 95) and Commercial Off-The-Shelf (COTS) components. Several issues regarding fault tolerance are presented and mechanisms to achieve fault tolerance by software active replication in Ada 95 are discussed. The Multi-μ architecture, based on a specifically proposed Fault Tolerance Manager (FTManager), is then described. Finally, some considerations are made about the work being done and essential future developments.

Avaliação e a Qualidade das Práticas de Inclusão para Alunos com PEA: Escala LAQI (Louisiana Autism Quality Indicators)

Dissertação apresentada à Escola Superior de Educação de Lisboa para obtenção de grau de mestre em Educação Especial, domínio Cognição e Multideficiência

Detection and diagnosis solutions for fault-tolerant VSI

This paper presents solutions for fault detection and diagnosis of two-level, three phase voltage-source inverter (VSI) topologies with IGBT devices. The proposed solutions combine redundant standby VSI structures and contactors (or relays) to improve the fault-tolerant capabilities of power electronics in applications with safety requirements. The suitable combination of these elements gives the inverter the ability to maintain energy processing in the occurrence of several failure modes, including short-circuit in IGBT devices, thus extending its reliability and availability. A survey of previously developed fault-tolerant VSI structures and several aspects of failure modes, detection and isolation mechanisms within VSI is first discussed. Hardware solutions for the protection of power semiconductors with fault detection and diagnosis mechanisms are then proposed to provide conditions to isolate and replace damaged power devices (or branches) in real time. Experimental results from a prototype are included to validate the proposed solutions.

Contextual and individual indicators associated with the presence of teeth in adults

OBJECTIVE The objective of this study was to analyze whether socioeconomic conditions and the period of availability of fluoridated water are associated with the number of teeth present.METHODSThis cross-sectional study analyzed data from 1,720 adults between 20 and 59 years of age who resided in Florianópolis, SC, Southern Brazil, in 2009. The outcome investigated was the self-reported number of teeth present. The individual independent variables included gender, age range, skin color, number of years of schooling, and per capita household income. The duration of residence was used as a control variable. The contextual exposures included the period of availability of fluoridated water to the households and the socioeconomic variable for the census tracts, which was created from factor analysis of the tract’s mean income, education level, and percentage of households with treated water. Multilevel logistic regression was performed and inter-level interactions were tested.RESULTS Residents in intermediate and poorer areas and those with fluoridated water available for less time exhibited the presence of fewer teeth compared with those in better socioeconomic conditions and who had fluoridated water available for a longer period (OR = 1.02; 95%CI 1.01;1.02). There was an association between the period of availability of fluoridated water, per capita household income and number of years of education. The proportion of individuals in the poorer and less-educated stratum, which had fewer teeth present, was higher in regions where fluoridated water had been available for less time.CONCLUSIONS Poor socioeconomic conditions and a shorter period of availability of fluoridated water were associated with the probability of having fewer teeth in adulthood. Public policies aimed at reducing socioeconomic inequalities and increasing access to health services such as fluoridation of the water supply may help to reduce tooth loss in the future.

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

The 1998 Faial earthquake, Azores: Evidence for a transform fault associated with the Nubia-Eurasia plate boundary?

With very few exceptions, M > 4 tectonic earthquakes in the Azores show normal fault solution and occur away from the islands. Exceptionally, the 1998 shock was pure strike-slip and occurred within the northern edge of the Pico-Faial Ridge. Fault plane solutions show two possible planes of rupture striking ENE-WSW (dextral) and NNW-SSE (sinistral). The former has not been recognised in the Azores, but is parallel to the transform direction related to the relative motion between the Eurasia and Nubia plates. Therefore, the main question we address in the present study is: do transform faults related to the Eurasia/Nubia plate boundary exist in the Azores? Knowing that the main source of strain is related to plate kinematics, we conclude that the sinistral strike-slip NNW-SSE fault plane solution is not consistent with either the fault dip (ca. 65, which is typical of a normal fault) or the ca. ENE-WSW direction of maximum extension; both are consistent with a normal fault, as observed in most major earthquakes on faults striking around NNW-SSE in the Azores. In contrast, the dextral strike-slip ENE-WSW fault plane solution is consistent with the transform direction related to the anticlockwise rotation of Nubia relative to Eurasia. Altogether, tectonic data, measured ground motion, observed destruction, and modelling are consistent with a dextral strike-slip source fault striking ENE-WSW. Furthermore, the bulk clockwise rotation measured by GPS is typical of bookshelf block rotations observed at the termination of such master strike-slip faults. Therefore, we suggest that the 1998 earthquake can be related to the WSW termination of a transform (ENE-WSW fault plane solution) associated with the Nubia-Eurasia diffuse plate boundary. (C) 2014 Elsevier B.V. All rights reserved.

Real time fault injection using a modified debugging infrastructure

Dependability is a critical factor in computer systems, requiring high quality validation & verification procedures in the development stage. At the same time, digital devices are getting smaller and access to their internal signals and registers is increasingly complex, requiring innovative debugging methodologies. To address this issue, most recent microprocessors include an on-chip debug (OCD) infrastructure to facilitate common debugging operations. This paper proposes an enhanced OCD infrastructure with the objective of supporting the verification of fault-tolerant mechanisms through fault injection campaigns. This upgraded on-chip debug and fault injection (OCD-FI) infrastructure provides an efficient fault injection mechanism with improved capabilities and dynamic behavior. Preliminary results show that this solution provides flexibility in terms of fault triggering and allows high speed real-time fault injection in memory elements

Real time fault injection using enhanced OCD -- a performance analysis

Fault injection is frequently used for the verification and validation of dependable systems. When targeting real time microprocessor based systems the process becomes significantly more complex. This paper proposes two complementary solutions to improve real time fault injection campaign execution, both in terms of performance and capabilities. The methodology is based on the use of the on-chip debug mechanisms present in modern electronic devices. The main objective is the injection of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented and compared in terms of performance gain and logic overhead.

Using NEXUS compliant debuggers for real time fault injection on microprocessors

As electronic devices get smaller and more complex, dependability assurance is becoming fundamental for many mission critical computer based systems. This paper presents a case study on the possibility of using the on-chip debug infrastructures present in most current microprocessors to execute real time fault injection campaigns. The proposed methodology is based on a debugger customized for fault injection and designed for maximum flexibility, and consists of injecting bit-flip type faults on memory elements without modifying or halting the target application. The debugger design is easily portable and applicable to different architectures, providing a flexible and efficient mechanism for verifying and validating fault tolerant components.

Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

Quality indicators in the education of children with profound Intellectual and multiple disabilities

Todas as crianças, independentemente das suas necessidades, deveriam ter acesso a uma educação de qualidade e a serem incluídas nas suas famílias e comunidades. Esta afirmação inclui as crianças mais vulneráveis, em particular as crianças com dificuldades intelectuais e multideficiência. Os resultados da investigação sobre a educação de crianças com dificuldades intelectuais e multideficiência ainda não produziram até ao momento informação suficiente que possa ser usada para desenvolver indicadores de qualidade para a avaliação das práticas e dos serviços. A investigação nesta área é limitada por constrangimentos éticos, dificuldades na determinação de amostras e desafios metodológicos, sendo reduzido o número de estudos capaz de produzir a informação necessária. Este artigo tem como objetivo discutir fatores que contribuam para a qualidade do envolvimento de crianças com dificuldades intelectuais e multideficiência em atividades educativas, com base na experiência das autoras e na informação disponível que tem sido publicada sobre este assunto. Com base nesta discussão é sugerido um conjunto de indicadores que poderão ajudar os profissionais a dirigir as suas observações para a qualidade da oferta educativa e para aspetos significativos dos desempenhos das crianças quando envolvidas em atividades curriculares.

A framework for fault tolerant real time systems based on reconfigurable FPGAs

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

Business micro-location: factors, preferences and indicators to assess the influence factors

The paper presents a study on business micro-location behaviour as well as corresponding factors of influence, conducted in two metropolitan areas, Bucharest-Ilfov (Romania) and Greater Porto (Portugal). By business micro-location we refer to a specific site such as a building or facility, accommodating a business within a small, compact geographical area (e.g. metropolitan area). At this geographical scale, the macroeconomic layer factors were excluded, applicable when discern between regions or countries. The factors derived from location theory and previous empirical studies were surveyed, completing a cross-sectional analysis in order to find out the specific weights of the location factors and preferences, by region and by industry. Based on already established firms’ feedback on location, the specific weights were granted by each industry to the main location factors, types of areas, and types of accommodation facilities. The authors also suggested a model to integrate these results into a Geographical Information System (GIS).