Novel hardwired distributive tactile sensing system for medical applications

This thesis described the research carried out on the development of a novel hardwired tactile sensing system tailored for the application of a next generation of surgical robotic and clinical devices, namely a steerable endoscope with tactile feedback, and a surface plate for patient posture and balance. Two case studies are examined. The first is a one-dimensional sensor for the steerable endoscope retrieving shape and ‘touch’ information. The second is a two-dimensional surface which interprets the three-dimensional motion of a contacting moving load. This research can be used to retrieve information from a distributive tactile sensing surface of a different configuration, and can interpret dynamic and static disturbances. This novel approach to sensing has the potential to discriminate contact and palpation in minimal invasive surgery (MIS) tools, and posture and balance in patients. The hardwired technology uses an embedded system based on Field Programmable Gate Arrays (FPGA) as the platform to perform the sensory signal processing part in real time. High speed robust operation is an advantage from this system leading to versatile application involving dynamic real time interpretation as described in this research. In this research the sensory signal processing uses neural networks to derive information from input pattern from the contacting surface. Three neural network architectures namely single, multiple and cascaded were introduced in an attempt to find the optimum solution for discrimination of the contacting outputs. These architectures were modelled and implemented into the FPGA. With the recent introduction of modern digital design flows and synthesis tools that essentially take a high-level sensory processing behaviour specification for a design, fast prototyping of the neural network function can be achieved easily. This thesis outlines the challenge of the implementations and verifications of the performances.

The immune system as drug target

The immune system is perhaps the largest yet most diffuse and distributed somatic system in vertebrates. It plays vital roles in fighting infection and in the homeostatic control of chronic disease. As such, the immune system in both pathological and healthy states is a prime target for therapeutic interventions by drugs-both small-molecule and biologic. Comprising both the innate and adaptive immune systems, human immunity is awash with potential unexploited molecular targets. Key examples include the pattern recognition receptors of the innate immune system and the major histocompatibility complex of the adaptive immune system. Moreover, the immune system is also the source of many current and, hopefully, future drugs, of which the prime example is the monoclonal antibody, the most exciting and profitable type of present-day drug moiety. This brief review explores the identity and synergies of the hierarchy of drug targets represented by the human immune system, with particular emphasis on the emerging paradigm of systems pharmacology. © the authors, publisher and licensee Libertas Academica Limited.

DC power line communication based on power/signal dual modulation in phase shift full bridge converters

For intelligent DC distributed power systems, data communication plays a vital role in system control and device monitoring. To achieve communication in a cost effective way, power/signal dual modulation (PSDM), a method that integrates data transmission with power conversion, can be utilized. In this paper, an improved PSDM method using phase shift full bridge (PSFB) converter is proposed. This method introduces a phase control based freedom in the conventional PSFB control loop to realize communication using the same power conversion circuit. In this way, decoupled data modulation and power conversion are realized without extra wiring and coupling units, and thus the system structure is simplified. More importantly, the signal intensity can be regulated by the proposed perturbation depth, and so this method can adapt to different operating conditions. Application of the proposed method to a DC distributed power system composed of several PSFB converters is discussed. A 2kW prototype system with an embedded 5kbps communication link has been implemented, and the effectiveness of the method is verified by experimental results.

Online Alpha Wave detector: an Embedded hardware-software implementation

The recent trend on embedded system development opens a new prospect for applications that in the past were not possible. The eye tracking for sleep and fatigue detection has become an important and useful application in industrial and automotive scenarios since fatigue is one of the most prevalent causes of earth-moving equipment accidents. Typical applications such as cameras, accelerometers and dermal analyzers are present on the market but have some inconvenient. This thesis project has used EEG signal, particularly, alpha waves, to overcome them by using an embedded software-hardware implementation to detect these signals in real time

Demonstrador para rede tempo-real HaRTES

A utilização de sistemas embutidos distribuídos em diversas áreas como a robótica, automação industrial e aviónica tem vindo a generalizar-se no decorrer dos últimos anos. Este tipo de sistemas são compostos por vários nós, geralmente designados por sistemas embutidos. Estes nós encontram-se interligados através de uma infra-estrutura de comunicação de forma a possibilitar a troca de informação entre eles de maneira a concretizar um objetivo comum. Por norma os sistemas embutidos distribuídos apresentam requisitos temporais bastante exigentes. A tecnologia Ethernet e os protocolos de comunicação, com propriedades de tempo real, desenvolvidos para esta não conseguem associar de uma forma eficaz os requisitos temporais das aplicações de tempo real aos requisitos Quality of Service (QoS) dos diferentes tipos de tráfego. O switch Hard Real-Time Ethernet Switching (HaRTES) foi desenvolvido e implementado com o objetivo de solucionar estes problemas devido às suas capacidades como a sincronização de fluxos diferentes e gestão de diferentes tipos de tráfego. Esta dissertação apresenta a adaptação de um sistemas físico de modo a possibilitar a demonstração do correto funcionamento do sistema de comunicação, que será desenvolvido e implementado, utilizando um switch HaRTES como o elemento responsável pela troca de informação na rede entre os nós. O desempenho da arquitetura de rede desenvolvida será também testada e avaliada.

Phobos: The design and implementation of embedded software for a low cost radar warning receiver

This portfolio thesis describes work undertaken by the author under the Engineering Doctorate program of the Institute for System Level Integration. It was carried out in conjunction with the sponsor company Teledyne Defence Limited. A radar warning receiver is a device used to detect and identify the emissions of radars. They were originally developed during the Second World War and are found today on a variety of military platforms as part of the platform’s defensive systems. Teledyne Defence has designed and built components and electronic subsystems for the defence industry since the 1970s. This thesis documents part of the work carried out to create Phobos, Teledyne Defence’s first complete radar warning receiver. Phobos was designed to be the first low cost radar warning receiver. This was made possible by the reuse of existing Teledyne Defence products, commercial off the shelf hardware and advanced UK government algorithms. The challenges of this integration are described and discussed, with detail given of the software architecture and the development of the embedded application. Performance of the embedded system as a whole is described and qualified within the context of a low cost system.

Solution to reduce nonlinearity in LTE RoF system for an efficient das topology:a brief review

In this paper, a review on radio-over-fiber (RoF) technology is conducted to support the exploding growth of mobile broadband. An RoF system will provide a platform for distributed antenna system (DAS) as a fronthaul of long term evolution (LTE) technology. A higher splitting ratio from a macrocell is required to support large DAS topology, hence higher optical launch power (OLP) is the right approach. However, high OLP generates undesired nonlinearities, namely the stimulated Brillouin scattering (SBS). Three different aspects of solving the SBS process are covered in this paper, where the solutions ultimately provided an additional 4 dB link budget.

Average-case analysis of power consumption in embedded systems

Power efficiency is one of the most important constraints in the design of embedded systems since such systems are generally driven by batteries with limited energy budget or restricted power supply. In every embedded system, there are one or more processor cores to run the software and interact with the other hardware components of the system. The power consumption of the processor core(s) has an important impact on the total power dissipated in the system. Hence, the processor power optimization is crucial in satisfying the power consumption constraints, and developing low-power embedded systems. A key aspect of research in processor power optimization and management is “power estimation”. Having a fast and accurate method for processor power estimation at design time helps the designer to explore a large space of design possibilities, to make the optimal choices for developing a power efficient processor. Likewise, understanding the processor power dissipation behaviour of a specific software/application is the key for choosing appropriate algorithms in order to write power efficient software. Simulation-based methods for measuring the processor power achieve very high accuracy, but are available only late in the design process, and are often quite slow. Therefore, the need has arisen for faster, higher-level power prediction methods that allow the system designer to explore many alternatives for developing powerefficient hardware and software. The aim of this thesis is to present fast and high-level power models for the prediction of processor power consumption. Power predictability in this work is achieved in two ways: first, using a design method to develop power predictable circuits; second, analysing the power of the functions in the code which repeat during execution, then building the power model based on average number of repetitions. In the first case, a design method called Asynchronous Charge Sharing Logic (ACSL) is used to implement the Arithmetic Logic Unit (ALU) for the 8051 microcontroller. The ACSL circuits are power predictable due to the independency of their power consumption to the input data. Based on this property, a fast prediction method is presented to estimate the power of ALU by analysing the software program, and extracting the number of ALU-related instructions. This method achieves less than 1% error in power estimation and more than 100 times speedup in comparison to conventional simulation-based methods. In the second case, an average-case processor energy model is developed for the Insertion sort algorithm based on the number of comparisons that take place in the execution of the algorithm. The average number of comparisons is calculated using a high level methodology called MOdular Quantitative Analysis (MOQA). The parameters of the energy model are measured for the LEON3 processor core, but the model is general and can be used for any processor. The model has been validated through the power measurement experiments, and offers high accuracy and orders of magnitude speedup over the simulation-based method.

Controlo de um gerador hidroeléctrico utilizado na recuperação de energia numa conduta de abastecimento de água

O presente trabalho pretende contribuir para a melhoria da eficiência dos sistemas de transporte e distribuição de água, possível de conseguir através da recuperação de energia potencial que, em certas situações, existe em excesso em condutas gravíticas. Sendo uma questão já abordada em diversos estudos, as poupanças de energia a que poderá conduzir, justificam a análise de todas as oportunidades, em especial no nosso País, cuja dependência energética do exterior é bem conhecida. Todavia, a implementação de soluções que recorrem à instalação de turbinas em condutas de abastecimento de água, causam naturalmente alguma apreensão às respectivas entidades gestoras, uma vez que pode pôr em causa a integridade das condutas e, em consequência, o abastecimento de água. Neste contexto, o estudo de modelos de controlo específicos para os referidos equipamentos poderá ser um contributo para a implementação mais alargada das soluções de melhoria da eficiência de sistemas de abastecimento de água, através da instalação de geradores hidroeléctricos, que terão a dupla função de controlo de caudal e produção de energia. O estudo e simulação dos modelos de controlo contidos neste trabalho permite concluir que é possível garantir a segurança das condutas e produzir energia eléctrica com turbinas nelas instaladas. Interessa assim aprofundar este tipo de estudos de forma a conseguir modelos de controlo que, com as premissas indicadas, possibilitem a optimização da produção de energia.

Meta-heuristics self-configuration for scheduling

Scheduling resolution requires the intervention of highly skilled human problemsolvers. This is a very hard and challenging domain because current systems are becoming more and more complex, distributed, interconnected and subject to rapidly changing. A natural Autonomic Computing evolution in relation to Current Computing is to provide systems with Self-Managing ability with a minimum human interference. This paper addresses the resolution of complex scheduling problems using cooperative negotiation. A Multi-Agent Autonomic and Meta-heuristics based framework with self-configuring capabilities is proposed.

Projecto de uma câmara em rede em FPGA

Trabalho Final de Mestrado para obtenção do grau de Mestre em Engenharia de Electrónica e Telecomunicações

Actuador linear para teste de teclas na indústria automóvel

As indústrias de componentes e acessórios automóveis são um elo fundamental no processo produtivo da indústria automóvel. Neste leque industrial encontra-se a Preh Portugal, Lda, como empresa fornecedora de componentes electrónicos, mais concretamente, painéis de controlo de climatização. Os painéis fornecidos pela Preh aos seus clientes encontram-se sujeitos a rigorosos testes de qualidade e funcionalidade. Neste sentido o teste funcional das teclas surge, relacionando o curso da tecla em função de uma força actuante. Esta relação está comprometida com uma curva característica padrão para o tipo de tecla. Para além destes compromissos, também é necessário que a tecla feche e abra o seu contacto eléctrico. Esta tese foca-se no desenvolvimento do teste de teclas, apresentando uma alteração ao sistema actual com a introdução de um sistema embebido, no intuito de flexibilizar o sistema de teste e reduzindo custos. O sistema embebido pretende dar capacidade de processamento ao teste e, desta forma, substituir o actual computador como elemento de processamento. A solução implementada consistiu numa mudança estrutural, através da inclusão do sistema embebido entre o computador e o sistema de deslocamento. Passando o foco central do processo de teste a residir no sistema embebido, este tem de estabelecer comunicações com os restantes elementos intervenientes no teste. Estabelece comunicações série RS-232 com o sistema de deslocamento (leitura do curso e força na tecla), Ethernet com o computador (comandos, parâmetros e resultados) e CAN com o painel de controlo de climatização (fecho/abertura do contacto eléctrico). A concretização deste projecto resultou numa nova estrutura e aplicação, a qual é facilmente integrada na linha de produção com as vantagens de ser menos onerosa e mais flexível, conforme o pretendido.

Controlador dedicado de Ecrãs LCD/TFT

Para dar resposta aos grandes avanços tecnológicos e, consequentemente, à postura mais exigente dos clientes, a empresa Francisco Parracho – Electrónica Industrial, Lda., que tem actividade no ramo dos elevadores, decidiu introduzir no mercado um controlador dedicado de ecrãs Liquid Crystal Display / Thin Film Transistor (LCD / TFT). O objectivo é substituir um sistema suportado por um computador, caracterizado pelas suas elevadas dimensões e custos, mas incontornável até à data, nomeadamente para resoluções de ecrã elevadas. E assim nasceu este trabalho. Com uma selecção criteriosa de todos os componentes e, principalmente, sem funcionalidades inúteis, obteve-se um sistema embebido com dimensões e custos bem mais reduzidos face ao seu opositor. O ecrã apontado para este projecto é um Thin Film Transistor – Liquid Crystal Display (TFT-LCD) da Sharp de 10.4” de qualidade industrial, com uma resolução de 800 x 600 píxeis a 18 bits por píxel. Para tal, foi escolhido um micro-controlador da ATMEL, um AVR de 32 bits que, entre outras características, possui um controlador LCD que suporta resoluções até 2048 x 2048 píxeis, de 1 a 24 bits por píxel. Atendendo ao facto deste produto ser inserido na área dos elevadores, as funcionalidades, quer a nível do hardware quer a nível do software, foram projectadas para este âmbito. Contudo, o conceito aqui exposto é adjacente a quaisquer outras áreas onde este produto se possa aplicar, até porque o software está feito para se tornar bem flexível. Com a ajuda de um kit de desenvolvimento, foram validados os drivers dos controladores e periféricos base deste projecto. De seguida, aplicou-se esse software numa placa de circuito impresso, elaborada no âmbito deste trabalho, para que fossem cumpridos todos os requisitos requeridos pela empresa patrocinadora: - Apresentação de imagens no ecrã consoante o piso; - Possibilidade de ter um texto horizontalmente deslizante;Indicação animada do sentido do elevador; - Representação do piso com deslizamento vertical; - Descrição sumária do directório de pisos também com deslizamento vertical; - Relógio digital; - Leitura dos conteúdos pretendidos através de um cartão SD/MMC; - Possibilidade de actualização dos conteúdos via USB flash drive.

High Performance Multi-Standard Architecture for DCT Computation in H.264/AVC High Profile and HEVC Codecs

A new high performance architecture for the computation of all the DCT operations adopted in the H.264/AVC and HEVC standards is proposed in this paper. Contrasting to other dedicated transform cores, the presented multi-standard transform architecture is supported on a completely configurable, scalable and unified structure, that is able to compute not only the forward and the inverse 8×8 and 4×4 integer DCTs and the 4×4 and 2×2 Hadamard transforms defined in the H.264/AVC standard, but also the 4×4, 8×8, 16×16 and 32×32 integer transforms adopted in HEVC. Experimental results obtained using a Xilinx Virtex-7 FPGA demonstrated the superior performance and hardware efficiency levels provided by the proposed structure, which outperforms its more prominent related designs by at least 1.8 times. When integrated in a multi-core embedded system, this architecture allows the computation, in real-time, of all the transforms mentioned above for resolutions as high as the 8k Ultra High Definition Television (UHDTV) (7680×4320 @ 30fps).