Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Design and optimization of FinFETs for ultra-low-voltage analog applications

In this paper, we analyze the enormous potential of engineering source/drain extension (SDE) regions in FinFETs for ultra-low-voltage (ULV) analog applications. SDE region design can simultaneously improve two key analog figures of merit (FOM)-intrinsic de gain (A(vo)) and cutoff frequency (f(T)) for 60 and 30 nm FinFETs operated at low drive current (J(ds) = 5 mu A/mu m). The improved Avo and fT are nearly twice compared to those of devices with abrupt SDE regions. The influence of the SDE region profile and its impact on analog FOM is extensively analyzed. Results show that SDE region optimization provides an additional degree of freedom apart from device parameters (fin width and aspect ratio) to design future nanoscale analog devices. The results are analyzed in terms of spacer-to-straggle ratio a new design parameter for SDE engineered devices. This paper provides new opportunities for realizing future ULV/low-power analog design with FinFETs.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

Analog performance of double gate SOI transistors

Double gate fully depleted silicon-on-insulator (DGSOI) is recognized as a possible solution when the physical gate length L-G reduces to 25nm for the 65nm node on the ITRS CMOS roadmap. In this paper, scaling guidelines are introduced to optimally design a nanoscale DGSOI. For this reason, the sensitivity of gain, f(T) and f(max) to each of the key geometric and technological parameters of the DGSOI are assessed and quantified using MixedMode simulation. The impact of the parasitic resistance and capacitance on analog device performance is systematically analysed. By comparing analog performance with a single gate (SG), it has been found that intrinsic gain in DGSOI is 4 times higher but its fT was found to be comparable to that of SGSOI at different regions of transistor operation. However, the extracted fmax in SG SOI was higher (similar to 40%) compared to DGSOI due to its lower capacitance.

Multidimensional operator multipliers

We introduce multidimensional Schur multipliers and characterise them, generalising well-known results by Grothendieck and Peller. We define a multidimensional version of the two-dimensional operator multipliers studied recently by Kissin and Shulman. The multidimensional operator multipliers are defined as elements of the minimal tensor product of several C *-algebras satisfying certain boundedness conditions. In the case of commutative C*-algebras, the multidimensional operator multipliersreduce to continuousmul-tidimensional Schur multipliers. We show that the multiplierswith respect to some given representations of the corresponding C*-algebrasdo not change if the representations are replaced by approximately equivalent ones. We establish a non-commutative and multidimensional version of the characterisations by Grothendieck and Peller which shows that universal operator multipliers can be obtained ascertain weak limits of elements of the algebraic tensor product of the corresponding C *-algebras.

Compactness properties of operator multipliers

We continue the study of multidimensional operator multipliers initiated in~cite{jtt}. We introduce the notion of the symbol of an operator multiplier. We characterise completely compact operator multipliers in terms of their symbol as well as in terms of approximation by finite rank multipliers. We give sufficient conditions for the sets of compact and completely compact multipliers to coincide and characterise the cases where an operator multiplier in the minimal tensor product of two C*-algebras is automatically compact. We give a description of multilinear modular completely compact completely bounded maps defined on the direct product of finitely many copies of the C*-algebra of compact operators in terms of tensor products, generalising results of Saar

Closable multipliers

Let $(X,\mu)$ and $(Y,\nu)$ be standard measure spaces. A function $\nph\in L^\infty(X\times Y,\mu\times\nu)$ is called a (measurable) Schur multiplier if the map $S_\nph$, defined on the space of Hilbert-Schmidt operators from $L_2(X,\mu)$ to $L_2(Y,\nu)$ by multiplying their integral kernels by $\nph$, is bound-ed in the operator norm. The paper studies measurable functions $\nph$ for which $S_\nph$ is closable in the norm topology or in the weak* topology. We obtain a characterisation of w*-closable multipliers and relate the question about norm closability to the theory of operator synthesis. We also study multipliers of two special types: if $\nph$ is of Toeplitz type, that is, if $\nph(x,y)=f(x-y)$, $x,y\in G$, where $G$ is a locally compact abelian group, then the closability of $\nph$ is related to the local inclusion of $f$ in the Fourier algebra $A(G)$ of $G$. If $\nph$ is a divided difference, that is, a function of the form $(f(x)-f(y))/(x-y)$, then its closability is related to the ``operator smoothness'' of the function $f$. A number of examples of non closable, norm closable and w*-closable multipliers are presented.

Multipliers of multidimensional Fourier algebras

Let $G$ be a locally compact $\sigma$-compact group. Motivated by an earlier notion for discrete groups due to Effros and Ruan, we introduce the multidimensional Fourier algebra $A^n(G)$ of $G$. We characterise the completely bounded multidimensional multipliers associated with $A^n(G)$ in several equivalent ways. In particular, we establish a completely isometric embedding of the space of all $n$-dimensional completely bounded multipliers into the space of all Schur multipliers on $G^{n+1}$ with respect to the (left) Haar measure. We show that in the case $G$ is amenable the space of completely bounded multidimensional multipliers coincides with the multidimensional Fourier-Stieltjes algebra of $G$ introduced by Ylinen. We extend some well-known results for abelian groups to the multidimensional setting.

How crucial is back gate misalignment/oversize in double gate MOSFETs for ultra-low-voltage analog/rf applications?

In the present work, by investigating the influence of source/drain (S/D) extension region engineering (also known as gate-underlap architecture) in planar Double Gate (DG) SOI MOSFETs, we offer new design insights to achieve high tolerance to gate misalignment/oversize in nanoscale devices for ultra-low-voltage (ULV) analog/rf applications. Our results show that (i) misaligned gate-underlap devices perform significantly better than DC devices with abrupt source/drain junctions with identical misalignment, (ii) misaligned gate underlap performance (with S/D optimization) exceeds perfectly aligned DG devices with abrupt S/D regions and (iii) 25% back gate misalignment can be tolerated without any significant degradation in cut-off frequency (f(T)) and intrinsic voltage gain (A(VO)). Gate-underlap DG devices designed with spacer-to-straggle ratio lying within the range 2.5 to 3.0 show best tolerance to misaligned/oversize back gate and indeed are better than self-aligned DG MOSFETs with non-underlap (abrupt) S/D regions. Impact of gate length and silicon film thickness scaling is also discussed. These results are very significant as the tolerable limit of misaligned/oversized back gate is considerably extended and the stringent process control requirements to achieve self-alignment can be relaxed for nanoscale planar ULV DG MOSFETs operating in weak-inversion region. The present work provides new opportunities for realizing future ULV analog/rf design with nanoscale gate-underlap DG MOSFETs. (C) 2008 Elsevier Ltd. All rights reserved.