Apparatus and method for heat-run test on high-power PWM converters with low energy expenditure

Before installation, a voltage source converter is usually subjected to heat-run test to verify its thermal design and performance under load. For heat-run test, the converter needs to be operated at rated voltage and rated current for a substantial length of time. Hence, such tests consume huge amount of energy in case of high-power converters. Also, the capacities of the source and loads available in the research and development (R&D) centre or the production facility could be inadequate to conduct such tests. This paper proposes a method to conduct heat-run tests on high-power, pulse width modulated (PWM) converters with low energy consumption. The experimental set-up consists of the converter under test and another converter (of similar or higher rating), both connected in parallel on the ac side and open on the dc side. Vector-control or synchronous reference frame control is employed to control the converters such that one draws certain amount of reactive power and the other supplies the same; only the system losses are drawn from the mains. The performance of the controller is validated through simulation and experiments. Experimental results, pertaining to heat-run tests on a high-power PWM converter, are presented at power levels of 25 kVA to 150 kVA.

An 8-to-1 bit 1-MS/s SAR ADC With VGA and Integrated Data Compression for Neural Recording

Low power consumption per channel and data rate minimization are two key challenges which need to be addressed in future generations of neural recording systems (NRS). Power consumption can be reduced by avoiding unnecessary processing whereas data rate is greatly decreased by sending spike time-stamps along with spike features as opposed to raw digitized data. Dynamic range in NRS can vary with time due to change in electrode-neuron distance or background noise, which demands adaptability. An analog-to-digital converter (ADC) is one of the most important blocks in a NRS. This paper presents an 8-bit SAR ADC in 0.13-mu m CMOS technology along with input and reference buffer. A novel energy efficient digital-to-analog converter switching scheme is proposed, which consumes 37% less energy than the present state-of-the-art. The use of a ping-pong input sampling scheme is emphasized for multichannel input to alleviate the bandwidth requirement of the input buffer. To reduce the data rate, the A/D process is only enabled through the in-built background noise rejection logic to ensure that the noise is not processed. The ADC resolution can be adjusted from 8 to 1 bit in 1-bit step based on the input dynamic range. The ADC consumes 8.8 mu W from 1 V supply at 1 MS/s speed. It achieves effective number of bits of 7.7 bits and FoM of 42.3 fJ/conversion-step.

A Three-Level Common-Mode Voltage Eliminated Inverter With Single DC Supply Using Flying Capacitor Inverter and Cascaded H-Bridge

A three-level common-mode voltage eliminated inverter with single dc supply using flying capacitor inverter and cascaded H-bridge has been proposed in this paper. The three phase space vector polygon formed by this configuration and the polygon formed by the common-mode eliminated states have been discussed. The entire system is simulated in Simulink and the results are experimentally verified. This system has an advantage that if one of devices in the H-bridge fails, the system can still be operated as a normal three-level inverter at full power. This inverter has many other advantages like use of single dc supply, making it possible for a back-to-back grid-tied converter application, improved reliability, etc.

Speed control of brushed DC motor for low cost electric cars

As petrol prices are going up in developing countries in upcoming decades low cost electric cars will become more and more popular in developing world. One of the main deciding factors for success of electric cars specially in developing world in upcoming decades will be its cost. This paper shows a cost effective method to control the speed of low cost brushed D.C. motor by combining a IC 555 Timer with a High Boost Converter. The main purpose of using High Boost Converter since electric cars needs high voltage and current which a High Boost Converter can provide even with low battery supply.

A Seventeen-level Inverter With a Single DC-link For Motor Drives

In the present paper, a novel topology for generating a 17-level inverter using three-level flying capacitor inverter and cascaded H-bridge modules with floating capacitors. The proposed circuit is analyzed and various aspects of it are presented in the paper. This circuit is experimentally verified and the results are shown. The stability of the capacitor balancing algorithm has been verified during sudden acceleration. This circuit has many pole voltage redundancies. This circuit has an advantage of balancing all the capacitor voltages instantaneously by switching through the redundancies. Another advantage of this topology is its ability to generate all the 17 pole voltages from a single DC link which enables back to back converter operation. Also, the proposed inverter can be operated at all load power factors and modulation indices. Another advantage is, if one of the H-bridges fail, the inverter can still be operated at full load with reduced number of levels.

Common-Mode and Differential-Mode Active Damping for PWM Rectifiers

Modern pulse-width-modulated (PWM) rectifiers use LC L filters that can be applied in both the common mode and differential mode to obtain high-performance filtering. Interaction between the passive L and C components in the filter leads to resonance oscillations. These oscillations need to be damped either by the passive damping or active damping. The passive damping increases power loss and can reduce the effectiveness of the filter. Methods of active damping, using control strategy, are lossless while maintaining the effectiveness of the filters. In this paper, an active damping strategy is proposed to damp the oscillations in both line-to-line and line-to-ground. An approach based on pole placement by the state feedback is used to actively damp both the differential-and common-mode filter oscillations. Analytical expressions for the state-feedback controller gains are derived for both continuous and discrete-time model of the filter. Tradeoff in selection of the active damping gain on the lower order power converter harmonics is analyzed using a weighted admittance function. Experimental results on a 10-kVA laboratory prototype PWM rectifier are presented. The results validate the effectiveness of the active damping method, and the tradeoff in the settings of the damping gain.

Minimum switching loss pulse width modulation for reduced power conversion loss in reactive power compensators

Advanced bus-clamping switching sequences, which employ an active vector twice in a subcycle, are used to reduce line current distortion and switching loss in a space vector modulated voltage source converter. This study evaluates minimum switching loss pulse width modulation (MSLPWM), which is a combination of such sequences, for static reactive power compensator (STATCOM) application. It is shown that MSLPWM results in a significant reduction in device loss over conventional space vector pulse width modulation. Experimental verification is presented at different power levels of up to 150 kVA.

Experimental Investigation on Switching Characteristics of High-Current Insulated Gate Bipolar Transistors at Low Currents

Insulated gate bipolar transistors (IGBTs) are used in high-power voltage-source converters rated up to hundreds of kilowatts or even a few megawatts. Knowledge of device switching characteristics is required for reliable design and operation of the converters. Switching characteristics are studied widely at high current levels, and corresponding data are available in datasheets. But the devices in a converter also switch low currents close to the zero crossings of the line currents. Further, the switching behaviour under these conditions could significantly influence the output waveform quality including zero crossover distortion. Hence, the switching characteristics of high-current IGBTs (300-A and 75-A IGBT modules) at low load current magnitudes are investigated experimentally in this paper. The collector current, gate-emitter voltage and collector-emitter voltage are measured at various low values of current (less than 10% of the device rated current). A specially designed in-house constructed coaxial current transformer (CCT) is used for device current measurement without increasing the loop inductance in the power circuit. Experimental results show that the device voltage rise time increases significantly during turn-off transitions at low currents.

Common-Mode Injection PWM for Parallel Converters

The ac-side terminal voltages of parallel-connected converters are different if the line reactive drops of the individual converters are different. This could result either from differences in per-phase inductances or from differences in the line currents of the converters. In such cases, the modulating signals are different for the converters. Hence, the common-mode (CM) voltages for the converters, injected by conventional space vector pulsewidth modulation (CSVPWM) to increase dc-bus utilization, are different. Consequently, significant low-frequency zero-sequence circulating currents result. This paper proposes a new modulation method for parallel-connected converters with unequal terminal voltages. This method does not cause low-frequency zero-sequence circulating currents and is comparable with CSVPWM in terms of dc-bus utilization and device power loss. Experimental results are presented at a power level of 150 kVA from a circulating-power test setup, where the differences in converter terminal voltages are quite significant.

Low-frequency dc bus ripple cancellation in single phase pulse-width modulation inverters

This study presents a topology for a single-phase pulse-width modulation (PWM) converter which achieves low-frequency ripple reduction in the dc bus even when there are grid frequency variations. A hybrid filter is introduced to absorb the low-frequency current ripple in the dc bus. The control strategy for the proposed filter does not require the measurement of the dc bus ripple current. The design criteria for selecting the filter components are also presented in this study. The effectiveness of the proposed circuit has been tested and validated experimentally. A smaller dc-link capacitor is sufficient to keep the low-frequency bus ripple to an acceptable range in the proposed topology.

Experimental Investigation on Switching Characteristics of High-Current Insulated Gate Bipolar Transistors at Low Currents

Insulated gate bipolar transistors (IGBTs) are used in high-power voltage-source converters rated up to hundreds of kilowatts or even a few megawatts. Knowledge of device switching characteristics is required for reliable design and operation of the converters. Switching characteristics are studied widely at high current levels, and corresponding data are available in datasheets. But the devices in a converter also switch low currents close to the zero crossings of the line currents. Further, the switching behaviour under these conditions could significantly influence the output waveform quality including zero crossover distortion. Hence, the switching characteristics of high-current IGBTs (300-A and 75-A IGBT modules) at low load current magnitudes are investigated experimentally in this paper. The collector current, gate-emitter voltage and collector-emitter voltage are measured at various low values of current (less than 10% of the device rated current). A specially designed in-house constructed coaxial current transformer (CCT) is used for device current measurement without increasing the loop inductance in the power circuit. Experimental results show that the device voltage rise time increases significantly during turn-off transitions at low currents.

Experimental results on low cost microcontroller based DC drive implementation

This paper presents the experimental results for an attractive control scheme implementation using an 8 bit microcontroller. The power converter involved is a 3 phase full controlled bridge rectifier. A single quadrant DC drive has been realized and results have been presented for both open and closed loop implementations.

Deciphering complex patterns of class-I HLA-peptide cross-reactivity via hierarchical grouping

T-cell responses in humans are initiated by the binding of a peptide antigen to a human leukocyte antigen (HLA) molecule. The peptide-HLA complex then recruits an appropriate T cell, leading to cell-mediated immunity. More than 2000 HLA class-I alleles are known in humans, and they vary only in their peptide-binding grooves. The polymorphism they exhibit enables them to bind a wide range of peptide antigens from diverse sources. HLA molecules and peptides present a complex molecular recognition pattern, as many peptides bind to a given allele and a given peptide can be recognized by many alleles. A powerful grouping scheme that not only provides an insightful classification, but is also capable of dissecting the physicochemical basis of recognition specificity is necessary to address this complexity. We present a hierarchical classification of 2010 class-I alleles by using a systematic divisive clustering method. All-pair distances of alleles were obtained by comparing binding pockets in the structural models. By varying the similarity thresholds, a multilevel classification was obtained, with 7 supergroups, each further subclassifying to yield 72 groups. An independent clustering performed based only on similarities in their epitope pools correlated highly with pocket-based clustering. Physicochemical feature combinations that best explain the basis of clustering are identified. Mutual information calculated for the set of peptide ligands enables identification of binding site residues contributing to peptide specificity. The grouping of HLA molecules achieved here will be useful for rational vaccine design, understanding disease susceptibilities and predicting risk of organ transplants.

Filter Configuration and PWM Method For Single-Phase Inverters With Reduced Conducted EMI Noise

Electromagnetic interference (EMI) noise is one of the major issues during design of grid-tied power converters. A novel LCL filter topology for a single-phase pulsewidth modulation (PWM) rectifier that makes use of bipolar PWM method is proposed for a single-phase to three-phase motor drive power converter. The proposed topology eliminates high dv/dt from the dc-bus common-mode (CM) voltage by making it sinusoidal. Hence, the high-frequency CM current injection to the ground and the motor-side CM current are minimized. The proposed filter configuration makes the system insensitive to circuit non-idealities such as mismatch in inductors values, unequal turn-on and turn-off delays, and dead-time mismatch between the inverter legs. Different variants of the filter topology are compared to establish the effectiveness of the proposed circuit. Experimental results based on the EMI measurement on the grid side and the CM current measurement on the motor side are presented for a 5-kW motor drive. It is shown that the proposed filter topology reduces the EMI noise level by about 35 dB.

Electroluminescence in Molecular Junctions: A Diagrammatic Approach

We compute electroluminescent signal in a current carrying single molecule junction using a superoperator formalism. Liouville space loop diagrams are used to identify all density matrix pathways that emit photons via the electroluminescence process. A frequency resolved spectrum is expressed in terms of the various Pock space states of the isolated molecule that participate in the creation and subsequent recombination of exciton. Application is made to a multilevel Coulomb blockade model system and to a gold-benzene-1,4-dithiol-gold molecular junction.