Hybrid LMS-LMF algorithm for adaptive echo cancellation

The coefficients of an echo canceller with a near-end section and a far-end section are usually updated with the same updating scheme, such as the LMS algorithm. A novel scheme is proposed for echo cancellation that is based on the minimisation of two different cost functions, i.e. one for the near-end section and a different one for the far-end section. The approach considered leads to a substantial improvement in performance over the LMS algorithm when it is applied to both sections of the echo canceller. The convergence properties of the algorithm are derived. The proposed scheme is also shown to be robust to noise variations. Simulation results confirm the superior performance of the new algorithm.

A self-structured adaptive decision feedback equalizer

In a decision feedback equalizer (DFE), the structural parameters, including the decision delay, the feedforward filter (FFF), and feedback filter (FBF) lengths, must be carefully chosen, as they greatly influence the performance. Although the FBF length can be set as the channel memory, there is no closed-form expression for the FFF length and decision delay. In this letter, first we analytically show that the two-dimensional search for the optimum FFF length and decision delay can be simplified to a one-dimensional search and then describe a new adaptive DFE where the optimum structural parameters can he self-adapted.

Adaptive data echo cancellation using cost function adaptation

For a digital echo canceller it is desirable to reduce the adaptation time, during which the transmission of useful data is not possible. LMS is a non-optimal algorithm in this case as the signals involved are statistically non-Gaussian. Walach and Widrow (IEEE Trans. Inform. Theory 30 (2) (March 1984) 275-283) investigated the use of a power of 4, while other research established algorithms with arbitrary integer (Pei and Tseng, IEEE J. Selected Areas Commun. 12(9)(December 1994) 1540-1547) or non-quadratic power (Shah and Cowan, IEE.Proc.-Vis. Image Signal Process. 142 (3) (June 1995) 187-191). This paper suggests that continuous and automatic, adaptation of the error exponent gives a more satisfactory result. The family of cost function adaptation (CFA) stochastic gradient algorithm proposed allows an increase in convergence rate and, an improvement of residual error. As special case the staircase CFA algorithm is first presented, then the smooth CFA is developed. Details of implementations are also discussed. Results of simulation are provided to show the properties of the proposed family of algorithms. (C) 2000 Elsevier Science B.V. All rights reserved.

Adaptability in organisms and artifacts: A multi level perspective on adaptive processes

Abstract Adaptability to changing circumstances is a key feature of living creatures. Understanding such adaptive processes is central to developing successful autonomous artifacts. In this paper two perspectives are brought to bear on the issue of adaptability. The first is a short term perspective which looks at adaptability in terms of the interactions between the agent and the environment. The second perspective involves a hierarchical evolutionary model which seeks to identify higher-order forms of adaptability based on the concept of adaptive meta-constructs. Task orientated and agent-centered models of adaptive processes in artifacts are considered from these two perspectives. The former isrepresented by the fitness function approach found in evolutionary learning, and the latter in terms of the concepts of empowerment and homeokinesis found in models derived from the self-organizing systems approach. A meta-construct approach to adaptability based on the identification of higher level meta-metrics is also outlined. 2009 Published by Elsevier B.V.

Linear QR architecture for a single chip adaptive beamformer

This paper presents the design of a novel single chip adaptive beamformer capable of performing 50 Gflops, (Giga-floating-point operations/second). The core processor is a QR array implemented on a fully efficient linear systolic architecture, derived using a mapping that allows individual processors for boundary and internal cell operations. In addition, the paper highlights a number of rapid design techniques that have been used to realise this system. These include an architecture synthesis tool for quickly developing the circuit architecture and the utilisation of a library of parameterisable silicon intellectual property (IP) cores, to rapidly develop detailed silicon designs.