Modelling the Performance of Flexible Substrates for Lead-Free Applications

In this paper, the performance of flexible substrates for lead-free applications was studied using finite element method (FEM). Firstly, the thermal induced stress in the flex substrate during the lead free solder reflow process was predicted. The shear stress at the interface between the copper track and flex was plotted. This shear stress increases with the thickness of the copper track. Secondly, an ACF flip chip was taken as a typical lead-free application of the flex substrate. The reflow effect on the reliability of ACF interconnections was analyzed. Higher stress was identified along the interface between the conductive particle and the metallization, and the interfacial stress increases with the reflow peak temperature and the coefficient of thermal expansion (CTE) of the adhesive. The moisture effect on the reliability of ACF joints were studied using a macro-micro modeling technique, the predominantly tensile stress found at the interface between the conductive particle and metallization could reduce the contact area and even cause the electrical failure. Modeling results are consistent with the findings in the experimental work

Macro-Micro Modelling Analysis for High Density Packaged Flip Chips

A wide range of flip chip technologies with solder or adhesives have become dominant solutions for high density packaging applications due to the excellent electrical performance, high I/O density and good thermal performance. This paper discusses the use of modeling technique to predict the reliability of high density packaged flip chips in the humid environment. Reliability assessment is discussed for flip chip package at ultra-fine pitch with anisotropic conductive film (ACF). The purpose of this modeling work is to understand the role that moisture plays in the failure of ACF flip chips. A macro-micro 3D finite element modeling technique was used in order to make the multi-length-scale modeling of the ACF flip chip possible. Modeling results are consistent with the findings in the experimental work

Moisture Effects on the Reliability of Anisotropic Conductive Films

Anisotropic conductive film (ACF) which consists of an adhesive epoxy matrix and randomly distributed conductive particles are widely used as the connection material for electronic devices with high I/O counts. However, for the semiconductor industry the reliability of the ACF is still a major concern due to a lack of experimental reliability data. This paper reports an investigation into the moisture effects on the reliability of ACF interconnections in the flip-chip-on-flex (FCOF) applications. A macro-micro 3D finite element modeling technique was used in order to make the multi-length-scale modeling of the ACF flip chip possible. The purposes of this modeling work was to understand the role that moisture plays in the failure of ACF flip chips, and to look into the influence of physical properties and geometric characteristics, such as the coefficient of the moisture expansion (CME), Young's modulus of the adhesive matrix and the bump height on the reliability of the ACF interconnections in a humid environment. Simulation results suggest that moisture-induced swelling of the adhesive matrix is the major cause of the ACF joint opening. Modeling results are consistent with the findings in the experimental work.

Decision support systems for eco-friendly electronic products

This paper discusses an optimisation based decision support system and methodology for electronic packaging and product design and development which is capable of addressing in efficient manner specified environmental, reliability and cost requirements. A study which focuses on the design of a flip-chip package is presented. Different alternatives for the design of the flip-chip package are considered based on existing options for the applied underfill and volume of solder material used to form the interconnects. Variations in these design input parameters have simultaneous effect on package aspects such as cost, environmental impact and reliability. A decision system for the design of the flip-chip that uses numerical optimisation approach is used to identify the package optimal specification which satisfies the imposed requirements. The reliability aspect of interest is the fatigue of solder joints under thermal cycling. Transient nonlinear finite element analysis (FEA) is used to simulate the thermal fatigue damage in solder joints subject to thermal cycling. Simulation results are manipulated within design of experiments and response surface modelling framework to provide numerical model for reliability which can be used to quantify the package reliability. Assessment of the environmental impact of the package materials is performed by using so called Toxic Index (TI). In this paper we demonstrate the evaluation of the environmental impact only for underfill and lead-free solder materials. This evaluation is based on the amount of material per flip-chip package. Cost is the dominant factor in contemporary flip-chip packaging industry. In the optimisation based decision support system for the design of the flip-chip package, cost of materials which varies as a result of variations in the design parameters is considered.

Optimisation modelling for design of advanced interconnects

This paper describes a computational strategy for virtual design and prototyping of electronic components and assemblies. The design process is formulated as a design optimisation problem. The solution of this problem identifies not only the design which meets certain user specified requirements but also the design with the maximum possible improvement in particular aspects such as reliability, cost, etc. The modelling approach exploits numerical techniques for computational analysis (Finite Element Analysis) integrated with numerical methods for approximation, statistical analysis and optimisation. A software framework of modules that incorporates the required numerical techniques is developed and used to carry out the design optimisation modelling of fine-pitch flip-chip lead free solder interconnects.

Analyzing the performance of flexible substrates for lead-free applications

The performance of flexible substrates for lead-free applications was studied using finite element method (FEM). Firstly, the thermal induced stress in the flex substrate during the lead free solder reflow process was predicted. The shear stress at the interface between the copper track and flex was plotted. This shear stress increases with the thickness of the copper track and the thickness of the flex. Secondly, an anisotropic conductive film (ACF) flip chip was taken as a typical lead-free application of the flex substrate and the moisture effect on the reliability of ACF joints were studied using a 3D macro-micro modeling technique. It is found that the time to be saturated of an ACF flip chip is much dependent on the moisture diffusion rate in the polyimide substrate. The majority moisture diffuses into the ACF layer from the substrate side rather than the periphery of the ACF. The moisture induced stress was predicted and the predominant tensile stress was found at the interface between the conductive particle and metallization which could reduce the contact area and even cause the electrical failure

Review of the technology and reliability issues arising as optical interconnects migrate onto the circuit board

Light has the greatest information carrying potential of all the perceivable interconnect mediums; consequently, optical fiber interconnects rapidly replaced copper in telecommunications networks, providing bandwidth capacity far in excess of its predecessors. As a result the modern telecommunications infrastructure has evolved into a global mesh of optical networks with VCSEL’s (Vertical Cavity Surface Emitting Lasers) dominating the short-link markets, predominately due to their low-cost. This cost benefit of VCSELs has allowed optical interconnects to again replace bandwidth limited copper as bottlenecks appear on VSR (Very Short Reach) interconnects between co-located equipment inside the CO (Central-Office). Spurred by the successful deployment in the VSR domain and in response to both intra-board backplane applications and inter-board requirements to extend the bandwidth between IC’s (Integrated Circuits), current research is migrating optical links toward board level USR (Ultra Short Reach) interconnects. Whilst reconfigurable Free Space Optical Interconnect (FSOI) are an option, they are complicated by precise line-of-sight alignment conditions hence benefits exist in developing guided wave technologies, which have been classified into three generations. First and second generation technologies are based upon optical fibers and are both capable of providing a suitable platform for intra-board applications. However, to allow component assembly, an integral requirement for inter-board applications, 3rd generation Opto-Electrical Circuit Boards (OECB’s) containing embedded waveguides are desirable. Currently, the greatest challenge preventing the deployment of OECB’s is achieving the out-of-plane coupling to SMT devices. With the most suitable low-cost platform being to integrate the optics into the OECB manufacturing process, several research avenues are being explored although none to date have demonstrated sufficient coupling performance. Once in place, the OECB assemblies will generate new reliability issues such as assembly configurations, manufacturing tolerances, and hermetic requirements that will also require development before total off-chip photonic interconnection can truly be achieved

Reliability study of the electroless Ni–P layer against solder alloy

Copper (Cu) has been widely used in the under bump metallurgy of chip and substrate metallization for chip packaging. However, due to the rapid formation of Cu–Sn intermetallic compound (IMC) at the tin-based solder/Cu interface during solder reaction, the reliability of this type of solder joint is a serious concern. In this work, electroless nickel–phosphorous (Ni–P) layer was deposited on the Cu pad of the flexible substrate as a diffusion barrier between Cu and the solder materials. The deposition was carried out in a commercial acidic sodium hypophosphite bath at 85 °C for different pH values. It was found that for the same deposition time period, higher pH bath composition (mild acidic) yields thicker Ni–P layer with lower phosphorous content. Solder balls having composition 62%Sn–36%Pb–2%Ag were reflowed at 240 °C for 1 to 180 min on three types of electroless Ni–P layers deposited at the pH value of 4, 4.8 and 6, respectively. Thermal stability of the electroless Ni–P barrier layer against the Sn–36%Pb–2%Ag solder reflowed for different time periods was examined by scanning electron microscopy equipped with energy dispersed X-ray. Solder ball shear test was performed in order to find out the relationship between the mechanical strength of solder joints and the characteristics of the electroless Ni–P layer deposited. The layer deposited in the pH 4 acidic bath showed the weak barrier against reflow soldering whereas layer deposited in pH 6 acidic bath showed better barrier against reflow soldering. Mechanical strength of the joints were deteriorated quickly in the layer deposited at pH 4 acidic bath, which was found to be thin and has a high phosphorous content. From the cross-sectional studies and fracture surface analyses, it was found that the appearance of the dark crystalline phosphorous-rich Ni layer weakened the interface and hence lower solder ball shear strength. Ni–Sn IMC formed at the interfaces was found to be more stable at the low phosphorous content (∼14 at.%) layer. Electroless Ni–P deposited at mild acidic bath resulting phosphorous content of around 14 at.% is suggested as the best barrier layer for Sn–36%Pb–2%Ag solder.

Thermal-mechanical modelling of power electronic module packaging

In this paper the reliability of the isolation substrate and chip mountdown solder interconnect of power modules under thermal-mechanical loading has been analysed using a numerical modelling approach. The damage indicators such as the peel stress and the accumulated plastic work density in solder interconnect are calculated for a range of geometrical design parameters, and the effects of these parameters on the reliability are studied by using a combination of the finite element analysis (FEA) method and optimisation techniques. The sensitivities of the reliability of the isolation substrate and solder interconnect to the changes of the design parameters are obtained and optimal designs are studied using response surface approximation and gradient optimization method

High current density induced damage mechanisms in electronic solder joints: a state-of-the-art review

High current density induced damages such as electromigration in the on-chip interconnection /metallization of Al or Cu has been the subject of intense study over the last 40 years. Recently, because of the increasing trend of miniaturization of the electronic packaging that encloses the chip, electromigration as well as other high current density induced damages are becoming a growing concern for off-chip interconnection where low melting point solder joints are commonly used. Before long, a huge number of publications have been explored on the electromigration issue of solder joints. However, a wide spectrum of findings might confuse electronic companies/designers. Thus, a review of the high current induced damages in solder joints is timely right this moment. We have selected 6 major phenomena to review in this paper. They are (i) electromigration (mass transfer due electron bombardment), (ii) thermomigration (mass transfer due to thermal gradient), (iii) enhanced intermetallic compound growth, (iv) enhanced current crowding, (v) enhanced under bump metallisation dissolution and (vi) high Joule heating and (vii) solder melting. the damage mechanisms under high current stressing in the tiny solder joint, mentioned in the review article, are significant roadblocks to further miniaturization of electronics. Without through understanding of these failure mechanisms by experiments coupled with mathematical modeling work, further miniaturization in electronics will be jeopardized

Microwave curing for high density package

Summary form only given. Currently the vast majority of adhesive materials in electronic products are bonded using convection heating or infra-red as well as UV-curing. These thermal processing steps can take several hours to perform, slowing throughput and contributing a significant portion of the cost of manufacturing. With the demand for lighter, faster, and smaller electronic devices, there is a need for innovative material processing techniques and control methodologies. The increasing demand for smaller and cheaper devices pose engineering challenges in designing a curing systems that minimize the time required between the curing of devices in a production line, allowing access to the components during curing for alignment and testing. Microwave radiation exhibits several favorable characteristics and over the past few years has attracted increased academic and industrial attention as an alternative solution to curing of flip-chip underfills, bumps, glob top and potting cure, structural bonding, die attach, wafer processing, opto-electronics assembly as well as RF-ID tag bonding. Microwave energy fundamentally accelerates the cure kinetics of polymer adhesives. It provides a route to focus heat into the polymer materials penetrating the substrates that typically remain transparent. Therefore microwave energy can be used to minimise the temperature increase in the surrounding materials. The short path between the energy source and the cured material ensures a rapid heating rate and an overall low thermal budget. In this keynote talk, we will review the principles of microwave curing of materials for high density packing. Emphasis will be placed on recent advances within ongoing research in the UK on the realization of "open-oven" cavities, tailored to address existing challenges. Open-ovens do not require positioning of the device into the cavity through a movable door, hence being more suitable for fully automated processing. Further potential advantages of op- - en-oven curing include the possibility for simultaneous fine placement and curing of the device into a larger assembly. These capabilities promise productivity gains by combining assembly, placement and bonding into a single processing step. Moreover, the proposed design allows for selective heating within a large substrate, which can be useful particularly when the latter includes parts sensitive to increased temperatures.

Advanced microwave oven for rapid curing of encapsulant

The curing of a thermosetting polymer materials utilized on micro-electronics packaging applications can be performed using microwave systems. The use of microwave energy enables the cure process to be completed more rapidly than with alternative approaches due to the ability to heat volumetrically. Furthermore, advanced dual-section microwave systems enable curing of individual components on a chip-on-board assembly. The dielectric properties of thermosetting polymer materials, commonly used in microelectronics packaging applications, vary significantly with temperature and degree of cure. The heating rate within a material subjected to an electric field is primarily dependant on the dielectric loss properties of the material itself. This article examines the variation in dielectric properties of a commercially available encapsulant paste with frequency and temperature and the resulting influence on the cure process. The 'FAMOBS' dual section microwave system and its application to microelectronics manufacture are described. The measurement of the dielectric properties of 'Henkel EO1080' encapsulant paste uses a commercially available 'dielectric probe kit' and is described in this paper. The FAMOBS heating system is used to encapsulate a small op-amp chip. A numerical model formulated to assess the cure process in thermosetting polymer materials under microwave heating is outlined. Numerical results showing that the microwave processing systems is capable of rapidly and evenly curing thermosetting polymer materials are presented.

Open ended microwave oven for packaging

A novel open waveguide cavity resonator is presented for the combined variable frequency microwave curing of bumps, underfills and encapsulants, as well as the alignment of devices for fast flip-chip assembly, direct chip attach (DCA) or wafer-scale level packaging (WSLP). This technology achieves radio frequency (RF) curing of adhesives used in microelectronics, optoelectronics and medical devices with potential simultaneous micron-scale alignment accuracy and bonding of devices. In principle, the open oven cavity can be fitted directly onto a flip-chip or wafer scale bonder and, as such, will allow for the bonding of devices through localised heating thus reducing the risk to thermally sensitive devices. Variable frequency microwave (VFM) heating and curing of an idealised polymer load is numerically simulated using a multi-physics approach. Electro-magnetic fields within a novel open ended microwave oven developed for use in micro-electronics manufacturing applications are solved using a dedicated Yee scheme finite-difference time-domain (FDTD) solver. Temperature distribution, degree of cure and thermal stresses are analysed using an Unstructured Finite Volume method (UFVM) multi-physics package. The polymer load was meshed for thermophysical analysis, whilst the microwave cavity - encompassing the polymer load - was meshed for microwave irradiation. The two solution domains are linked using a cross mapping routine. The principle of heating using the evanescent fringing fields within the open-end of the cavity is demonstrated. A closed loop feedback routine is established allowing the temperature within a lossy sample to be controlled. A distribution of the temperature within the lossy sample is obtained by using a thermal imaging camera.

Integrated biomedical device for blood preparation

The separation of red blood cells from plasma flowing in microchannels is possible by bio-physical effects such as an axial migration effect and Zweifach-Fung bifurcation law. In the present study, subchannels are placed alongside a main channel to collect cells and plasma separately. The addition of a constriction in the main microchannel creates a local high shear force region, forcing the cells to migrate and concentrate towards the centre of the channel. The resulting lab-on-a-chip was manufactured using biocompatible materials. Purity efficiency was measured for mussel and human blood suspensions as different parameters including flow rate and geometries of parent and daughter channels were varied.

On the application of variable frequency microwave technology for processing of individual surface mount components

Dual-section variable frequency microwave systems enable rapid, controllable heating of materials within an individual surface mount component in a chip-on=board assembly. The ability to process devices individually allows components with disparate processing requirements to be mounted on the same assembly. The temperature profile induced by the microwave system can be specifically tailored to the needs of the component, allowing optimisation and degree of cure whilst minimising thermomechanical stresses. This paper presents a review of dual-section microwave technology and its application to curing of thermosetting polymer materials in microelectronics applications. Curing processes using both conventional and microwave technologies are assessed and compared. Results indicate that dual-section microwave systems are able to cure individual surface mount packages in a significantly shorter time, at the expense of an increase in thermomechanical stresses and a greater variation in degree of cure.