Real-time fault injection using enhanced on-chip debug infrastructures

The rapid increase in the use of microprocessor-based systems in critical areas, where failures imply risks to human lives, to the environment or to expensive equipment, significantly increased the need for dependable systems, able to detect, tolerate and eventually correct faults. The verification and validation of such systems is frequently performed via fault injection, using various forms and techniques. However, as electronic devices get smaller and more complex, controllability and observability issues, and sometimes real time constraints, make it harder to apply most conventional fault injection techniques. This paper proposes a fault injection environment and a scalable methodology to assist the execution of real-time fault injection campaigns, providing enhanced performance and capabilities. Our proposed solutions are based on the use of common and customized on-chip debug (OCD) mechanisms, present in many modern electronic devices, with the main objective of enabling the insertion of faults in microprocessor memory elements with minimum delay and intrusiveness. Different configurations were implemented starting from basic Components Off-The-Shelf (COTS) microprocessors, equipped with real-time OCD infrastructures, to improved solutions based on modified interfaces, and dedicated OCD circuitry that enhance fault injection capabilities and performance. All methodologies and configurations were evaluated and compared concerning performance gain and silicon overhead.

Reliability and availability in reconfigurable computing: a basis for a common solution

Dynamically reconfigurable SRAM-based field-programmable gate arrays (FPGAs) enable the implementation of reconfigurable computing systems where several applications may be run simultaneously, sharing the available resources according to their own immediate functional requirements. To exclude malfunctioning due to faulty elements, the reliability of all FPGA resources must be guaranteed. Since resource allocation takes place asynchronously, an online structural test scheme is the only way of ensuring reliable system operation. On the other hand, this test scheme should not disturb the operation of the circuit, otherwise availability would be compromised. System performance is also influenced by the efficiency of the management strategies that must be able to dynamically allocate enough resources when requested by each application. As those resources are allocated and later released, many small free resource blocks are created, which are left unused due to performance and routing restrictions. To avoid wasting logic resources, the FPGA logic space must be defragmented regularly. This paper presents a non-intrusive active replication procedure that supports the proposed test methodology and the implementation of defragmentation strategies, assuring both the availability of resources and their perfect working condition, without disturbing system operation.

Using SysML in systems design

System of systems involves several secondary systems working together with its creation gathering the knowledge of several distinct disciplines and teams, each one with their own background and methods, leading to a difficult communication between them. SysML, a language originated from UML, enables that communication, without background interference, with the use of a rich notation for systems design. This paper analyzes its use through the experience gained in the design of a chemical system with SysML.

FPGA-based weblab infrastructures guidelines and a prototype implementation example

Recent trends show an increasing number of weblabs, implemented at universities and schools, supporting practical training in technical courses and providing the ability to remotely conduct experiments. However, their implementation is typically based on individual architectures, unable of being reconfigured with different instruments/modules usually required by every experiment. In this paper, we discuss practical guidelines for implementing reconfigurable weblabs that support both local and remote control interfaces. The underlying infrastructure is based on reconfigurable, low-cost, FPGA-based boards supporting several peripherals that are used for the local interface. The remote interface is powered by a module capable of communicating with an Ethernet based network and that can either correspond to an internal core of the FPGA or an external device. These two approaches are discussed in the paper, followed by a practical implementation example.

Using remote lab networks to provide support to public secondary school education level

The advantages of networking are widely known in many areas (from business to personal ones). One particular area where networks have also proved their benefits is education. Taking the secondary school education level into account, some successful cases can be found in literature. In this paper we describe a particular remote lab network supporting physical experiments accessible to students of institutions geographically separated. The network architecture and application examples of using some of the available remote experiments are illustrated in detail.

Addressing software impact in the design of remote laboratories

Remote Laboratories or WebLabs constitute a first-order didactic resource in engineering faculties. However, in many cases, they lack a proper software design, both in the client and server side, which degrades their quality and academic usefulness. This paper presents the main characteristics of a Remote Laboratory, analyzes the software technologies to implement the client and server sides in a WebLab, and correlates these technologies with the characteristics to facilitate the selection of a technology to implement a WebLab. The results obtained suggest the adoption of a Service Oriented Laboratory Architecture-based approach for the design of future Remote Laboratories so that client-agnostic Remote Laboratories and Remote Laboratory composition are enabled. The experience with the real Remote Laboratory, WebLab-Deusto, is also presented.

On-line self-healing of circuits implemented on reconfigurable FPGAs

To boost logic density and reduce per unit power consumption SRAM-based FPGAs manufacturers adopted nanometric technologies. However, this technology is highly vulnerable to radiation-induced faults, which affect values stored in memory cells, and to manufacturing imperfections. Fault tolerant implementations, based on Triple Modular Redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like module placement, the effects of multi- bit upsets (MBU) or fault accumulation, have also to be addressed. In case of a fault occurrence the correct operation of the affected module must be restored and/or the current state of the circuit coherently re-established. A solution that enables the autonomous restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in real-time, while keeping the normal operation of the circuit, is presented in this paper.

A framework for self-healing radiation-tolerant implementations on reconfigurable FPGAs

To increase the amount of logic available in SRAM-based FPGAs manufacturers are using nanometric technologies to boost logic density and reduce prices. However, nanometric scales are highly vulnerable to radiation-induced faults that affect values stored in memory cells. Since the functional definition of FPGAs relies on memory cells, they become highly prone to this type of faults. Fault tolerant implementations, based on triple modular redundancy (TMR) infrastructures, help to keep the correct operation of the circuit. However, TMR is not sufficient to guarantee the safe operation of a circuit. Other issues like the effects of multi-bit upsets (MBU) or fault accumulation, have also to be addressed. Furthermore, in case of a fault occurrence the correct operation of the affected module must be restored and the current state of the circuit coherently re-established. A solution that enables the autonomous correct restoration of the functional definition of the affected module, avoiding fault accumulation, re-establishing the correct circuit state in realtime, while keeping the normal operation of the circuit, is presented in this paper.

A framework for fault tolerant real time systems based on reconfigurable FPGAs

To increase the amount of logic available to the users in SRAM-based FPGAs, manufacturers are using nanometric technologies to boost logic density and reduce costs, making its use more attractive. However, these technological improvements also make FPGAs particularly vulnerable to configuration memory bit-flips caused by power fluctuations, strong electromagnetic fields and radiation. This issue is particularly sensitive because of the increasing amount of configuration memory cells needed to define their functionality. A short survey of the most recent publications is presented to support the options assumed during the definition of a framework for implementing circuits immune to bit-flips induction mechanisms in memory cells, based on a customized redundant infrastructure and on a detection-and-fix controller.

A modified debugging infrastructure to assist real time fault injection campaigns

Fault injection is frequently used for the verification and validation of the fault tolerant features of microprocessors. This paper proposes the modification of a common on-chip debugging (OCD) infrastructure to add fault injection capabilities and improve performance. The proposed solution imposes a very low logic overhead and provides a flexible and efficient mechanism for the execution of fault injection campaigns, being applicable to different target system architectures.

How remote labs impact on course outcomes: various practices using VISIR

As technology is increasingly being seen as a facilitator to learning, open remote laboratories are increasingly available and in widespread use around the world. They provide some advantages over traditional hands-on labs or simulations. This paper presents the results of integrating the open remote laboratory VISIR into several courses, in various contexts and using various methodologies. These integrations, all related to higher education engineering, were designed by teachers with different perspectives to achieve a range of learning outcomes. The degree to which these VISIR-related outcomes were accomplished is discussed. The results reflect the levels of student engagement and learning and of teacher involvement. From the analysis, a connection between these two aspects was traced, although only related to the user profiles. VISIR is shown to be always of benefit for more motivated students, but this benefit can be maximized under particular conditions and characteristics.

Remote and mobile experimentation: pushing the boundaries of an ubiquitous learning place

Concepts like E-learning and M-learning are changing the traditional learning place. No longer restricted to well-defined physical places, education on Automation and other Engineering areas is entering the so-called ubiquitous learning place, where even the more practical knowledge (acquired at lab classes) is now moving into, due to emergent concepts such as Remote Experimentation or Mobile Experimentation. While Remote Experimentation is traditionally regarded as the remote access to real-world experiments through a simple web browser running on a PC connected to the Internet, Mobile Experimentation may be seen as the access to those same (or others) experiments, through mobile devices, used in M-learning contexts. These two distinct client types (PCs versus mobile devices) pose specific requirements for the remote lab infrastructure, namely the ability to tune the experiment interface according to the characteristics (e.g. display size) of the accessing device. This paper addresses those requirements, namely by proposing a new architecture for the remote lab infrastructure able to accommodate both Remote and Mobile Experimentation scenarios.

A self-healing real-time system based on run-time self-reconfiguration

The new generations of SRAM-based FPGA (field programmable gate array) devices are the preferred choice for the implementation of reconfigurable computing platforms intended to accelerate processing in real-time systems. However, FPGA's vulnerability to hard and soft errors is a major weakness to robust configurable system design. In this paper, a novel built-in self-healing (BISH) methodology, based on run-time self-reconfiguration, is proposed. A soft microprocessor core implemented in the FPGA is responsible for the management and execution of all the BISH procedures. Fault detection and diagnosis is followed by repairing actions, taking advantage of the dynamic reconfiguration features offered by new FPGA families. Meanwhile, modular redundancy assures that the system still works correctly

Management Driven Hybrid Multicast Framework for Content Aware Networks

The need for better adaptation of networks to transported flows has led to research on new approaches such as content aware networks and network aware applications. In parallel, recent developments of multimedia and content oriented services and applications such as IPTV, video streaming, video on demand, and Internet TV reinforced interest in multicast technologies. IP multicast has not been widely deployed due to interdomain and QoS support problems; therefore, alternative solutions have been investigated. This article proposes a management driven hybrid multicast solution that is multi-domain and media oriented, and combines overlay multicast, IP multicast, and P2P. The architecture is developed in a content aware network and network aware application environment, based on light network virtualization. The multicast trees can be seen as parallel virtual content aware networks, spanning a single or multiple IP domains, customized to the type of content to be transported while fulfilling the quality of service requirements of the service provider.

Fábrica das artes como projecto educativo: relatório de estágio

Relatório de Estágio submetido à Escola Superior de Teatro e Cinema para cumprimento dos requisitos necessários à obtenção do Grau de Mestre em Teatro – especialização Produção.