On efficient data integrity and data origin authentication for wireless sensor networks utilising block cipher design techniques

Analysis of the generic attacks and countermeasures for block cipher based message authentication code algorithms (MAC) in sensor applications is undertaken; the conclusions are used in the design of two new MAC constructs Quicker Block Chaining MAC1 (QBC-MAC1) and Quicker Block Chaining MAC2 (QBC-MAC2). Using software simulation we show that our new constructs point to improvements in usage of CPU instruction clock cycle and energy requirement when benchmarked against the de facto Cipher Block Chaining MAC (CBC-MAC) based construct used in the TinySec security protocol for wireless sensor networks.

Zone based systems design framework for the realisation of efficient block cipher based message authentication code algorithms

A zone based systems design framework is described and utilised in the implementation of a message authentication code (MAC) algorithm based on symmetric key block ciphers. The resulting block cipher based MAC algorithm may be used to provide assurance of the authenticity and, hence, the integrity of binary data. Using software simulation to benchmark against the de facto cipher block chaining MAC (CBC-MAC) variant used in the TinySec security protocol for wireless sensor networks and the NIST cipher block chaining MAC standard, CMAC; we show that our zone based systems design framework can lead to block cipher based MAC constructs that point to improvements in message processing efficiency, processing throughput and processing latency.

Applications of Satellite Earth Observations section - NEODAAS: Providing satellite data for efficient research

The NERC Earth Observation Data Acquisition and Analysis Service (NEODAAS) provides a central point of Earth Observation (EO) satellite data access and expertise for UK researchers. The service is tailored to individual users’ requirements to ensure that researchers can focus effort on their science, rather than struggling with correct use of unfamiliar satellite data.

NEODAAS: Providing satellite data for efficient research

The NERC Earth Observation Data Acquisition and Analysis Service (NEODAAS) provides a central point of Earth Observation (EO) satellite data access and expertise for UK researchers. The service is tailored to individual users’ requirements to ensure that researchers can focus effort on their science, rather than struggling with correct use of unfamiliar satellite data.

Efficient Non-Linear Idealisations of Aircraft Fuselage Panels in Compression

Aircraft fuselages are complex assemblies of thousands of components and as a result simulation models are highly idealised. In the typical design process, a coarse FE model is used to determine loads within the structure. The size of the model and number of load cases necessitates that only linear static behaviour is considered. This paper reports on the development of a modelling approach to increase the accuracy of the global model, accounting for variations in stiffness due to non-linear structural behaviour. The strategy is based on representing a fuselage sub-section with a single non-linear element. Large portions of fuselage structure are represented by connecting these non-linear elements together to form a framework. The non-linear models are very efficient, reducing computational time significantly

Contingent screening for down syndrome is an efficient alternative to non-disclosure sequential screening

Objective To present a first and second trimester Down syndrome screening strategy, whereby second-trimester marker determination is contingent on the first-trimester results. Unlike non-disclosure sequential screening (the Integrated test), which requires all women to have markers in both trimesters, this allows a large proportion of the women to complete screening in the first trimester. Methods Two first-trimester risk cut-offs defined three types of results: positive and referred for early diagnosis; negative with screening complete; and intermediate, needing second-trimester markers. Multivariate Gaussian modelling with Monte Carlo simulation was used to estimate the false-positive rate for a fixed 85% detection rate. The false-positive rate was evaluated for various early detection rates and early test completion rates. Model parameters were taken from the SURUSS trial. Results Completion of screening in the first trimester for 75% of women resulted in a 30% early detection rate and a 55% second trimester detected rate (net 85%) with a false-positive rate only 0.1% above that achievable by the Integrated test. The screen-positive rate was 0.1% in the first trimester and 4.7% for those continuing to be tested in the second trimester. If the early detection rate were to be increased to 45% or the early completion rate were to be increased to 80%, there would be a further 0.1% increase in the false-positive rate. Conclusion Contingent screening can achieve results comparable with the Integrated test but with earlier completion of screening for most women. Both strategies need to be evaluated in large-scale prospective studies particularly in relation to psychological impact and practicability.

Efficient FPGA Hardware Development: A Multi-Language Approach

This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high-level hardware design and efficient hardware implementation. The central idea of this framework is the integration of different hardware languages in a way that harnesses the best features of each language. This is illustrated in this paper by the integration of two hardware languages in the form of HIDE: a structured hardware language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog, and Handel-C: an ANSI C-like hardware language which allows software and hardware engineers alike to target FPGAs from high-level algorithmic descriptions. On the one hand, HIDE has proven to be very successful in the description and generation of highly optimised parameterisable FPGA circuits from geometric descriptions. On the other hand, Handel-C has also proven to be very successful in the rapid design and prototyping of FPGA circuits from algorithmic application descriptions. The proposed integrated framework hence harnesses HIDE for the generation of highly optimised circuits for regular parts of algorithms, while Handel-C is used as a top-level design language from which HIDE functionality is dynamically invoked. The overall message of this paper posits that there need not be an exclusive choice between different hardware design flows. Rather, an integrated framework where different design flows can seamlessly interoperate should be adopted. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware languages.