Photonic integrated circuits development: a universal transceiver for NG-PON2

In the last years there has been a clear evolution in the world of telecommunications, which goes from new services that need higher speeds and higher bandwidth, until a role of interactions between people and machines, named by Internet of Things (IoT). So, the only technology able to follow this growth is the optical communications. Currently the solution that enables to overcome the day-by-day needs, like collaborative job, audio and video communications and share of les is based on Gigabit-capable Passive Optical Network (G-PON) with the recently successor named Next Generation Passive Optical Network Phase 2 (NG-PON2). This technology is based on the multiplexing domain wavelength and due to its characteristics and performance becomes the more advantageous technology. A major focus of optical communications are Photonic Integrated Circuits (PICs). These can include various components into a single device, which simpli es the design of the optical system, reducing space and power consumption, and improves reliability. These characteristics make this type of devices useful for several applications, that justi es the investments in the development of the technology into a very high level of performance and reliability in terms of the building blocks. With the goal to develop the optical networks of future generations, this work presents the design and implementation of a PIC, which is intended to be a universal transceiver for applications for NG-PON2. The same PIC will be able to be used as an Optical Line Terminal (OLT) or an Optical Network Unit (ONU) and in both cases as transmitter and receiver. Initially a study is made of Passive Optical Network (PON) and its standards. Therefore it is done a theoretical overview that explores the materials used in the development and production of this PIC, which foundries are available, and focusing in SMART Photonics, the components used in the development of this chip. For the conceptualization of the project di erent architectures are designed and part of the laser cavity is simulated using Aspic™. Through the analysis of advantages and disadvantages of each one, it is chosen the best to be used in the implementation. Moreover, the architecture of the transceiver is simulated block by block through the VPItransmissionMaker™ and it is demonstrated its operating principle. Finally it is presented the PIC implementation.

Generating a state t-design by diagonal quantum circuits

We investigate protocols for generating a state t-design by using a fixed separable initial state and a diagonal-unitary t-design in the computational basis, which is a t-design of an ensemble of diagonal unitary matrices with random phases as their eigenvalues. We first show that a diagonal-unitary t-design generates a O (1/2(N))-approximate state t-design, where N is the number of qubits. We then discuss a way of improving the degree of approximation by exploiting non-diagonal gates after applying a diagonal-unitary t-design. We also show that it is necessary and sufficient to use O (log(2)(t)) -qubit gates with random phases to generate a diagonal-unitary t-design by diagonal quantum circuits, and that each multi-qubit diagonal gate can be replaced by a sequence of multi-qubit controlled-phase-type gates with discrete-valued random phases. Finally, we analyze the number of gates for implementing a diagonal-unitary t-design by non-diagonal two- and one-qubit gates. Our results provide a concrete application of diagonal quantum circuits in quantum informational tasks.

From Hardware Processes to asynchronous circuits via petri nets: An Application to Arbiter Design

International audience

Low-power high-performance SAR ADC design with digital calibration techniques

This dissertation presents the design of three high-performance successive-approximation-register (SAR) analog-to-digital converters (ADCs) using distinct digital background calibration techniques under the framework of a generalized code-domain linear equalizer. These digital calibration techniques effectively and efficiently remove the static mismatch errors in the analog-to-digital (A/D) conversion. They enable aggressive scaling of the capacitive digital-to-analog converter (DAC), which also serves as sampling capacitor, to the kT/C limit. As a result, outstanding conversion linearity, high signal-to-noise ratio (SNR), high conversion speed, robustness, superb energy efficiency, and minimal chip-area are accomplished simultaneously. The first design is a 12-bit 22.5/45-MS/s SAR ADC in 0.13-μm CMOS process. It employs a perturbation-based calibration based on the superposition property of linear systems to digitally correct the capacitor mismatch error in the weighted DAC. With 3.0-mW power dissipation at a 1.2-V power supply and a 22.5-MS/s sample rate, it achieves a 71.1-dB signal-to-noise-plus-distortion ratio (SNDR), and a 94.6-dB spurious free dynamic range (SFDR). At Nyquist frequency, the conversion figure of merit (FoM) is 50.8 fJ/conversion step, the best FoM up to date (2010) for 12-bit ADCs. The SAR ADC core occupies 0.06 mm2, while the estimated area the calibration circuits is 0.03 mm2. The second proposed digital calibration technique is a bit-wise-correlation-based digital calibration. It utilizes the statistical independence of an injected pseudo-random signal and the input signal to correct the DAC mismatch in SAR ADCs. This idea is experimentally verified in a 12-bit 37-MS/s SAR ADC fabricated in 65-nm CMOS implemented by Pingli Huang. This prototype chip achieves a 70.23-dB peak SNDR and an 81.02-dB peak SFDR, while occupying 0.12-mm2 silicon area and dissipating 9.14 mW from a 1.2-V supply with the synthesized digital calibration circuits included. The third work is an 8-bit, 600-MS/s, 10-way time-interleaved SAR ADC array fabricated in 0.13-μm CMOS process. This work employs an adaptive digital equalization approach to calibrate both intra-channel nonlinearities and inter-channel mismatch errors. The prototype chip achieves 47.4-dB SNDR, 63.6-dB SFDR, less than 0.30-LSB differential nonlinearity (DNL), and less than 0.23-LSB integral nonlinearity (INL). The ADC array occupies an active area of 1.35 mm2 and dissipates 30.3 mW, including synthesized digital calibration circuits and an on-chip dual-loop delay-locked loop (DLL) for clock generation and synchronization.

Improving DPA and DFA resistance of circuits using asynchronous logic

International audience

Toxicity of 2,3,7,8-tetrachlorodibenzo-p-dioxin (TCDD) in the developing male Wistar(Han) rat II: chronic dosing causes developmental delay

We have investigated whether fetal exposure to 2,3,7,8-tetrachlorodibenzo-p-dioxin (TCDD) causes defects in the male reproductive system of the rat, using chronically exposed rats to ensure continuous exposure of the fetus. 5-6 week old rats were exposed to control diet, or diet containing TCDD, to attain an average dose of 2.4, 8 and 46 ng TCDD kg-1 day-1 for twelve weeks, whereupon the rats were mated, and allowed to litter; rats were switched to control diet after parturition. Male offspring were allowed to develop until kills on PND70 (25 per group), or PND120 (all remaining animals). Offspring from the high dose group showed an increase in total litter loss, and the number of animals alive on post-natal day (PND) 4 in the high dose group was ~26% less than control. The high and medium dose offspring showed decreased weights at various ages. Balano-preputial separation was significantly delayed in all three dose groups, compared to control. There were no significant effects of maternal treatment when the offspring were subjected to a functional observational battery, or learning tests, with the exception that the high dose group showed a deficit in motor activity. 20 rats per group were mated to females, and there were no significant effects of maternal treatment on the fertility of these rats, nor on the F1 or F2 sex ratio. Sperm parameters at PND70 and 120 showed no significant effect of maternal treatment, with the exception that there was an increase in the proportion of abnormal sperm in the high dose group at PND70; this is associated with the developmental delay in puberty in this dose group. There were no remarkable findings of maternal treatment on organ weights, with the exception that testis weights were reduced by ~10% at PND70 (but not PND120), and although the experiment was sufficiently powered to detect small changes, ventral prostate weight was not reduced. There were no significant effects of maternal treatment upon histopathological comparison of high dose and control group organs. These data confirm that developmental exposure to TCDD shows no potent effect on adult sperm parameters or accessory sexual organs, but show that delay in BPS occurs after exposure to low doses of TCDD, and this is dependent upon whether TCDD is administered acutely or chronically.

17-Week Delay Surgery after Chemoradiation in Rectal Cancer with Complete Pathological Response

Neoadjuvant chemoradiation (CRT) followed by curative surgery still remains the standard of care for locally advanced rectal cancer (LARC). The main purpose of this multimodal treatment is to achieve a complete pathological tumor response (ypCR), with better survival. The surgery delay after CRT completion seems to increase tumor response and ypCR rate. Usually, time intervals range from 8 to 12 weeks, but the maximum tumor regression may not be seen in rectal adenocarcinomas until several months after CRT. About this issue, we report a case of a 52-year-old man with LARC treated with neoadjuvant CRT who developed, one month after RT completion, an acute myocardial infarction. The need to increase the interval between CRT and surgery for 17 weeks allowed a curative surgery without morbidity and an unexpected complete tumor response in the resected specimen (given the parameters presented in pelvic magnetic resonance imaging (MRI) performed 11 weeks after radiotherapy completion).

Components and circuits for tunneling diode based high frequency sources

Terahertz (THz) technology has been generating a lot of interest because of the potential applications for systems working in this frequency range. However, to fully achieve this potential, effective and efficient ways of generating controlled signals in the terahertz range are required. Devices that exhibit negative differential resistance (NDR) in a region of their current-voltage (I-V ) characteristics have been used in circuits for the generation of radio frequency signals. Of all of these NDR devices, resonant tunneling diode (RTD) oscillators, with their ability to oscillate in the THz range are considered as one of the most promising solid-state sources for terahertz signal generation at room temperature. There are however limitations and challenges with these devices, from inherent low output power usually in the range of micro-watts (uW) for RTD oscillators when milli-watts (mW) are desired. At device level, parasitic oscillations caused by the biasing line inductance when the device is biased in the NDR region prevent accurate device characterisation, which in turn prevents device modelling for computer simulations. This thesis describes work on I-V characterisation of tunnel diode (TD) and RTD (fabricated by Dr. Jue Wang) devices, and the radio frequency (RF) characterisation and small signal modelling of RTDs. The thesis also describes the design and measurement of hybrid TD oscillators for higher output power and the design and measurement of a planar Yagi antenna (fabricated by Khalid Alharbi) for THz applications. To enable oscillation free current-voltage characterisation of tunnel diodes, a commonly employed method is the use of a suitable resistor connected across the device to make the total differential resistance in the NDR region positive. However, this approach is not without problems as the value of the resistor has to satisfy certain conditions or else bias oscillations would still be present in the NDR region of the measured I-V characteristics. This method is difficult to use for RTDs which are fabricated on wafer due to the discrepancies in designed and actual resistance values of fabricated resistors using thin film technology. In this work, using pulsed DC rather than static DC measurements during device characterisation were shown to give accurate characteristics in the NDR region without the need for a stabilisation resistor. This approach allows for direct oscillation free characterisation for devices. Experimental results show that the I-V characterisation of tunnel diodes and RTD devices free of bias oscillations in the NDR region can be made. In this work, a new power-combining topology to address the limitations of low output power of TD and RTD oscillators is presented. The design employs the use of two oscillators biased separately, but with the combined output power from both collected at a single load. Compared to previous approaches, this method keeps the frequency of oscillation of the combined oscillators the same as for one of the oscillators. Experimental results with a hybrid circuit using two tunnel diode oscillators compared with a single oscillator design with similar values shows that the coupled oscillators produce double the output RF power of the single oscillator. This topology can be scaled for higher (up to terahertz) frequencies in the future by using RTD oscillators. Finally, a broadband Yagi antenna suitable for wireless communication at terahertz frequencies is presented in this thesis. The return loss of the antenna showed that the bandwidth is larger than the measured range (140-220 GHz). A new method was used to characterise the radiation pattern of the antenna in the E-plane. This was carried out on-wafer and the measured radiation pattern showed good agreement with the simulated pattern. In summary, this work makes important contributions to the accurate characterisation and modelling of TDs and RTDs, circuit-based techniques for power combining of high frequency TD or RTD oscillators, and to antennas suitable for on chip integration with high frequency oscillators.

Poor quality specimens delay detection of blood disorders in newborns

This sheet describes the right way to take a blood sample from a newborn infant.

Fractional variational problems depending on indefinite integrals and with delay

The aim of this paper is to exhibit a necessary and sufficient condition of optimality for functionals depending on fractional integrals and derivatives, on indefinite integrals and on presence of time delay. We exemplify with one example, where we nd analytically the minimizer.

An identification procedure of multi-input Wiener models for the distortion analysis of nonlinear circuits

In this contribution, a system identification procedure of a two-input Wiener model suitable for the analysis of the disturbance behavior of integrated nonlinear circuits is presented. The identified block model is comprised of two linear dynamic and one static nonlinear block, which are determined using an parameterized approach. In order to characterize the linear blocks, an correlation analysis using a white noise input in combination with a model reduction scheme is adopted. After having characterized the linear blocks, from the output spectrum under single tone excitation at each input a linear set of equations will be set up, whose solution gives the coefficients of the nonlinear block. By this data based black box approach, the distortion behavior of a nonlinear circuit under the influence of an interfering signal at an arbitrary input port can be determined. Such an interfering signal can be, for example, an electromagnetic interference signal which conductively couples into the port of consideration. © 2011 Author(s).

LHC main dipole magnet circuits: sustaining near-nominal beam energies

Crossing the Franco-Swiss border, the Large Hadron Collider (LHC), designed to collide 7 TeV proton beams, is the world's largest and most powerful particle accelerator the operation of which was originally intended to commence in 2008. Unfortunately, due to an interconnect discontinuity in one of the main dipole circuit's 13 kA superconducting busbars, a catastrophic quench event occurred during initial magnet training, causing significant physical system damage. Furthermore, investigation into the cause found that such discontinuities were not only present in the circuit in question, but throughout the entire LHC. This prevented further magnet training and ultimately resulted in the maximum sustainable beam energy being limited to approximately half that of the design nominal, 3.5-4 TeV, for the first three years of operation (Run 1, 2009-2012) and a major consolidation campaign being scheduled for the first long shutdown (LS 1, 2012-2014). Throughout Run 1, a series of studies attempted to predict the amount of post-installation training quenches still required to qualify each circuit to nominal-energy current levels. With predictions in excess of 80 quenches (each having a recovery time of 8-12+ hours) just to achieve 6.5 TeV and close to 1000 quenches for 7 TeV, it was decided that for Run 2, all systems be at least qualified for 6.5 TeV operation. However, even with all interconnect discontinuities scheduled to be repaired during LS 1, numerous other concerns regarding circuit stability arose. In particular, observations of an erratic behaviour of magnet bypass diodes and the degradation of other potentially weak busbar sections, as well as observations of seemingly random millisecond spikes in beam losses, known as unidentified falling object (UFO) events, which, if persist at 6.5 TeV, may eventually deposit sufficient energy to quench adjacent magnets. In light of the above, the thesis hypothesis states that, even with the observed issues, the LHC main dipole circuits can safely support and sustain near-nominal proton beam energies of at least 6.5 TeV. Research into minimising the risk of magnet training led to the development and implementation of a new qualification method, capable of providing conclusive evidence that all aspects of all circuits, other than the magnets and their internal joints, can safely withstand a quench event at near-nominal current levels, allowing for magnet training to be carried out both systematically and without risk. This method has become known as the Copper Stabiliser Continuity Measurement (CSCM). Results were a success, with all circuits eventually being subject to a full current decay from 6.5 TeV equivalent current levels, with no measurable damage occurring. Research into UFO events led to the development of a numerical model capable of simulating typical UFO events, reproducing entire Run 1 measured event data sets and extrapolating to 6.5 TeV, predicting the likelihood of UFO-induced magnet quenches. Results provided interesting insights into the involved phenomena as well as confirming the possibility of UFO-induced magnet quenches. The model was also capable of predicting that such events, if left unaccounted for, are likely to be commonplace or not, resulting in significant long-term issues for 6.5+ TeV operation. Addressing the thesis hypothesis, the following written works detail the development and results of all CSCM qualification tests and subsequent magnet training as well as the development and simulation results of both 4 TeV and 6.5 TeV UFO event modelling. The thesis concludes, post-LS 1, with the LHC successfully sustaining 6.5 TeV proton beams, but with UFO events, as predicted, resulting in otherwise uninitiated magnet quenches and being at the forefront of system availability issues.

Instabilities in threshold-diffusion equations with delay

The introduction of delays into ordinary or partial differential equation models is well known to facilitate the production of rich dynamics ranging from periodic solutions through to spatio-temporal chaos. In this paper we consider a class of scalar partial differential equations with a delayed threshold nonlinearity which admits exact solutions for equilibria, periodic orbits and travelling waves. Importantly we show how the spectra of periodic and travelling wave solutions can be determined in terms of the zeros of a complex analytic function. Using this as a computational tool to determine stability we show that delays can have very different effects on threshold systems with negative as opposed to positive feedback. Direct numerical simulations are used to confirm our bifurcation analysis, and to probe some of the rich behaviour possible for mixed feedback.

Inverted decoupling internal model control for square stable multivariable time delay systems

This paper presents a new tuning methodology of the main controller of an internal model control structure for n×n stable multivariable processes with multiple time delays based on the centralized inverted decoupling structure. Independently of the system size, very simple general expressions for the controller elements are obtained. The realizability conditions are provided and the specification of the closed-loop requirements is explained. A diagonal filter is added to the proposed control structure in order to improve the disturbance rejection without modifying the nominal set-point response. The effectiveness of the method is illustrated through different simulation examples in comparison with other works.

Architectural-Physical Co-Design of 3D CPUs with Micro-Fluidic Cooling

The performance, energy efficiency and cost improvements due to traditional technology scaling have begun to slow down and present diminishing returns. Underlying reasons for this trend include fundamental physical limits of transistor scaling, the growing significance of quantum effects as transistors shrink, and a growing mismatch between transistors and interconnects regarding size, speed and power. Continued Moore's Law scaling will not come from technology scaling alone, and must involve improvements to design tools and development of new disruptive technologies such as 3D integration. 3D integration presents potential improvements to interconnect power and delay by translating the routing problem into a third dimension, and facilitates transistor density scaling independent of technology node. Furthermore, 3D IC technology opens up a new architectural design space of heterogeneously-integrated high-bandwidth CPUs. Vertical integration promises to provide the CPU architectures of the future by integrating high performance processors with on-chip high-bandwidth memory systems and highly connected network-on-chip structures. Such techniques can overcome the well-known CPU performance bottlenecks referred to as memory and communication wall. However the promising improvements to performance and energy efficiency offered by 3D CPUs does not come without cost, both in the financial investments to develop the technology, and the increased complexity of design. Two main limitations to 3D IC technology have been heat removal and TSV reliability. Transistor stacking creates increases in power density, current density and thermal resistance in air cooled packages. Furthermore the technology introduces vertical through silicon vias (TSVs) that create new points of failure in the chip and require development of new BEOL technologies. Although these issues can be controlled to some extent using thermal-reliability aware physical and architectural 3D design techniques, high performance embedded cooling schemes, such as micro-fluidic (MF) cooling, are fundamentally necessary to unlock the true potential of 3D ICs. A new paradigm is being put forth which integrates the computational, electrical, physical, thermal and reliability views of a system. The unification of these diverse aspects of integrated circuits is called Co-Design. Independent design and optimization of each aspect leads to sub-optimal designs due to a lack of understanding of cross-domain interactions and their impacts on the feasibility region of the architectural design space. Co-Design enables optimization across layers with a multi-domain view and thus unlocks new high-performance and energy efficient configurations. Although the co-design paradigm is becoming increasingly necessary in all fields of IC design, it is even more critical in 3D ICs where, as we show, the inter-layer coupling and higher degree of connectivity between components exacerbates the interdependence between architectural parameters, physical design parameters and the multitude of metrics of interest to the designer (i.e. power, performance, temperature and reliability). In this dissertation we present a framework for multi-domain co-simulation and co-optimization of 3D CPU architectures with both air and MF cooling solutions. Finally we propose an approach for design space exploration and modeling within the new Co-Design paradigm, and discuss the possible avenues for improvement of this work in the future.