Using pMOS Pass-Gates to Boost SRAM Performance by Exploiting Strain Effects in Sub-20-nm FinFET Technologies

Strained fin is one of the techniques used to improve the devices as their size keeps reducing in new nanoscale nodes. In this paper, we use a predictive technology of 14 nm where pMOS mobility is significantly improved when those devices are built on top of long, uncut fins, while nMOS devices present the opposite behavior due to the combination of strains. We explore the possibility of boosting circuit performance in repetitive structures where long uncut fins can be exploited to increase fin strain impact. In particular, pMOS pass-gates are used in 6T complementary SRAM cells (CSRAM) with reinforced pull-ups. Those cells are simulated under process variability and compared to the regular SRAM. We show that when layout dependent effects are considered the CSRAM design provides 10% to 40% faster access time while keeping the same area, power, and stability than a regular 6T SRAM cell. The conclusions also apply to 8T SRAM cells. The CSRAM cell also presents increased reliability in technologies whose nMOS devices have more mismatch than pMOS transistors.

Method for electrical evaluation of graphene using a GFET structure

n this work, we explain a method to characterize graphene using electrical measurements in graphene field-effect transistors (GFET) devices. Our goal is to obtain the material electronic properties from the output characteristics of one GFET device. For the previous purpose, we will need to apply a physical model that allows us to correlate the electronic behavior of a GFET with the material properties.

Temperature performance of AlGaN/GaN MOS-HEMTs on Si substrates using Gd2O3 as gate dielectric

GaN based high electron mobility transistors have draw great attention due to its potential in high temperature, high power and high frequency applications [1, 2]. However, significant gate leakage current is still one of the issues which need to be solved to improve the performance and reliability of the devices [3]. Several research groups have contributed to solve this problem by using metal–oxide–semiconductor HEMTs (MOSHEMTs), with a thin dielectric layer, such as SiO2 [4], Al2O3 [5], HfO2 [6] and Gd2O3 [7] between the gate and the barrier layer on AlGaN/GaN heterostructures. Gd2O3 has shown low interfacial density of states(Dit) with GaN and a high dielectric constant and low electrical leakage currents [8], thus is considered as a promising candidate for the gate dielectrics on GaN. MOS-HEMTs using Gd2O3 grown by electron-beam heating [7] or molecular beam epitaxy (MBE) [8] on GaN or AlGan/GaN structure have been investigated, but further research is still needed in Gd2O3 based AlGaN/GaN MOSHEMTs.

Design and Simulation of Deep Nanometer SRAM Cells under Energy, Mismatch, and Radiation Constraints

La fiabilidad está pasando a ser el principal problema de los circuitos integrados según la tecnología desciende por debajo de los 22nm. Pequeñas imperfecciones en la fabricación de los dispositivos dan lugar ahora a importantes diferencias aleatorias en sus características eléctricas, que han de ser tenidas en cuenta durante la fase de diseño. Los nuevos procesos y materiales requeridos para la fabricación de dispositivos de dimensiones tan reducidas están dando lugar a diferentes efectos que resultan finalmente en un incremento del consumo estático, o una mayor vulnerabilidad frente a radiación. Las memorias SRAM son ya la parte más vulnerable de un sistema electrónico, no solo por representar más de la mitad del área de los SoCs y microprocesadores actuales, sino también porque las variaciones de proceso les afectan de forma crítica, donde el fallo de una única célula afecta a la memoria entera. Esta tesis aborda los diferentes retos que presenta el diseño de memorias SRAM en las tecnologías más pequeñas. En un escenario de aumento de la variabilidad, se consideran problemas como el consumo de energía, el diseño teniendo en cuenta efectos de la tecnología a bajo nivel o el endurecimiento frente a radiación. En primer lugar, dado el aumento de la variabilidad de los dispositivos pertenecientes a los nodos tecnológicos más pequeños, así como a la aparición de nuevas fuentes de variabilidad por la inclusión de nuevos dispositivos y la reducción de sus dimensiones, la precisión del modelado de dicha variabilidad es crucial. Se propone en la tesis extender el método de inyectores, que modela la variabilidad a nivel de circuito, abstrayendo sus causas físicas, añadiendo dos nuevas fuentes para modelar la pendiente sub-umbral y el DIBL, de creciente importancia en la tecnología FinFET. Los dos nuevos inyectores propuestos incrementan la exactitud de figuras de mérito a diferentes niveles de abstracción del diseño electrónico: a nivel de transistor, de puerta y de circuito. El error cuadrático medio al simular métricas de estabilidad y prestaciones de células SRAM se reduce un mínimo de 1,5 veces y hasta un máximo de 7,5 a la vez que la estimación de la probabilidad de fallo se mejora en varios ordenes de magnitud. El diseño para bajo consumo es una de las principales aplicaciones actuales dada la creciente importancia de los dispositivos móviles dependientes de baterías. Es igualmente necesario debido a las importantes densidades de potencia en los sistemas actuales, con el fin de reducir su disipación térmica y sus consecuencias en cuanto al envejecimiento. El método tradicional de reducir la tensión de alimentación para reducir el consumo es problemático en el caso de las memorias SRAM dado el creciente impacto de la variabilidad a bajas tensiones. Se propone el diseño de una célula que usa valores negativos en la bit-line para reducir los fallos de escritura según se reduce la tensión de alimentación principal. A pesar de usar una segunda fuente de alimentación para la tensión negativa en la bit-line, el diseño propuesto consigue reducir el consumo hasta en un 20 % comparado con una célula convencional. Una nueva métrica, el hold trip point se ha propuesto para prevenir nuevos tipos de fallo debidos al uso de tensiones negativas, así como un método alternativo para estimar la velocidad de lectura, reduciendo el número de simulaciones necesarias. Según continúa la reducción del tamaño de los dispositivos electrónicos, se incluyen nuevos mecanismos que permiten facilitar el proceso de fabricación, o alcanzar las prestaciones requeridas para cada nueva generación tecnológica. Se puede citar como ejemplo el estrés compresivo o extensivo aplicado a los fins en tecnologías FinFET, que altera la movilidad de los transistores fabricados a partir de dichos fins. Los efectos de estos mecanismos dependen mucho del layout, la posición de unos transistores afecta a los transistores colindantes y pudiendo ser el efecto diferente en diferentes tipos de transistores. Se propone el uso de una célula SRAM complementaria que utiliza dispositivos pMOS en los transistores de paso, así reduciendo la longitud de los fins de los transistores nMOS y alargando los de los pMOS, extendiéndolos a las células vecinas y hasta los límites de la matriz de células. Considerando los efectos del STI y estresores de SiGe, el diseño propuesto mejora los dos tipos de transistores, mejorando las prestaciones de la célula SRAM complementaria en más de un 10% para una misma probabilidad de fallo y un mismo consumo estático, sin que se requiera aumentar el área. Finalmente, la radiación ha sido un problema recurrente en la electrónica para aplicaciones espaciales, pero la reducción de las corrientes y tensiones de los dispositivos actuales los está volviendo vulnerables al ruido generado por radiación, incluso a nivel de suelo. Pese a que tecnologías como SOI o FinFET reducen la cantidad de energía colectada por el circuito durante el impacto de una partícula, las importantes variaciones de proceso en los nodos más pequeños va a afectar su inmunidad frente a la radiación. Se demuestra que los errores inducidos por radiación pueden aumentar hasta en un 40 % en el nodo de 7nm cuando se consideran las variaciones de proceso, comparado con el caso nominal. Este incremento es de una magnitud mayor que la mejora obtenida mediante el diseño de células de memoria específicamente endurecidas frente a radiación, sugiriendo que la reducción de la variabilidad representaría una mayor mejora. ABSTRACT Reliability is becoming the main concern on integrated circuit as the technology goes beyond 22nm. Small imperfections in the device manufacturing result now in important random differences of the devices at electrical level which must be dealt with during the design. New processes and materials, required to allow the fabrication of the extremely short devices, are making new effects appear resulting ultimately on increased static power consumption, or higher vulnerability to radiation SRAMs have become the most vulnerable part of electronic systems, not only they account for more than half of the chip area of nowadays SoCs and microprocessors, but they are critical as soon as different variation sources are regarded, with failures in a single cell making the whole memory fail. This thesis addresses the different challenges that SRAM design has in the smallest technologies. In a common scenario of increasing variability, issues like energy consumption, design aware of the technology and radiation hardening are considered. First, given the increasing magnitude of device variability in the smallest nodes, as well as new sources of variability appearing as a consequence of new devices and shortened lengths, an accurate modeling of the variability is crucial. We propose to extend the injectors method that models variability at circuit level, abstracting its physical sources, to better model sub-threshold slope and drain induced barrier lowering that are gaining importance in FinFET technology. The two new proposed injectors bring an increased accuracy of figures of merit at different abstraction levels of electronic design, at transistor, gate and circuit levels. The mean square error estimating performance and stability metrics of SRAM cells is reduced by at least 1.5 and up to 7.5 while the yield estimation is improved by orders of magnitude. Low power design is a major constraint given the high-growing market of mobile devices that run on battery. It is also relevant because of the increased power densities of nowadays systems, in order to reduce the thermal dissipation and its impact on aging. The traditional approach of reducing the voltage to lower the energy consumption if challenging in the case of SRAMs given the increased impact of process variations at low voltage supplies. We propose a cell design that makes use of negative bit-line write-assist to overcome write failures as the main supply voltage is lowered. Despite using a second power source for the negative bit-line, the design achieves an energy reduction up to 20% compared to a conventional cell. A new metric, the hold trip point has been introduced to deal with new sources of failures to cells using a negative bit-line voltage, as well as an alternative method to estimate cell speed, requiring less simulations. With the continuous reduction of device sizes, new mechanisms need to be included to ease the fabrication process and to meet the performance targets of the successive nodes. As example we can consider the compressive or tensile strains included in FinFET technology, that alter the mobility of the transistors made out of the concerned fins. The effects of these mechanisms are very dependent on the layout, with transistor being affected by their neighbors, and different types of transistors being affected in a different way. We propose to use complementary SRAM cells with pMOS pass-gates in order to reduce the fin length of nMOS devices and achieve long uncut fins for the pMOS devices when the cell is included in its corresponding array. Once Shallow Trench isolation and SiGe stressors are considered the proposed design improves both kinds of transistor, boosting the performance of complementary SRAM cells by more than 10% for a same failure probability and static power consumption, with no area overhead. While radiation has been a traditional concern in space electronics, the small currents and voltages used in the latest nodes are making them more vulnerable to radiation-induced transient noise, even at ground level. Even if SOI or FinFET technologies reduce the amount of energy transferred from the striking particle to the circuit, the important process variation that the smallest nodes will present will affect their radiation hardening capabilities. We demonstrate that process variations can increase the radiation-induced error rate by up to 40% in the 7nm node compared to the nominal case. This increase is higher than the improvement achieved by radiation-hardened cells suggesting that the reduction of process variations would bring a higher improvement.

Paper-like electronic displays: Large-area rubber-stamped plastic sheets of electronics and microencapsulated electrophoretic inks

Electronic systems that use rugged lightweight plastics potentially offer attractive characteristics (low-cost processing, mechanical flexibility, large area coverage, etc.) that are not easily achieved with established silicon technologies. This paper summarizes work that demonstrates many of these characteristics in a realistic system: organic active matrix backplane circuits (256 transistors) for large (≈5 × 5-inch) mechanically flexible sheets of electronic paper, an emerging type of display. The success of this effort relies on new or improved processing techniques and materials for plastic electronics, including methods for (i) rubber stamping (microcontact printing) high-resolution (≈1 μm) circuits with low levels of defects and good registration over large areas, (ii) achieving low leakage with thin dielectrics deposited onto surfaces with relief, (iii) constructing high-performance organic transistors with bottom contact geometries, (iv) encapsulating these transistors, (v) depositing, in a repeatable way, organic semiconductors with uniform electrical characteristics over large areas, and (vi) low-temperature (≈100°C) annealing to increase the on/off ratios of the transistors and to improve the uniformity of their characteristics. The sophistication and flexibility of the patterning procedures, high level of integration on plastic substrates, large area coverage, and good performance of the transistors are all important features of this work. We successfully integrate these circuits with microencapsulated electrophoretic “inks” to form sheets of electronic paper.

Oxide Semiconductors For Organic Opto-electronic Devices

Development of transparent oxide semiconductors (TOS) from Earth-abundant materials is of great interest for cost-effective thin film device applications, such as solar cells, light emitting diodes (LEDs), touch-sensitive displays, electronic paper, and transparent thin film transistors. The need of inexpensive or high performance electrode might be even greater for organic photovoltaic (OPV), with the goal to harvest renewable energy with inexpensive, lightweight, and cost competitive materials. The natural abundance of zinc and the wide bandgap ($sim$3.3 eV) of its oxide make it an ideal candidate. In this dissertation, I have introduced various concepts on the modulations of various surface, interface and bulk opto-electronic properties of ZnO based semiconductor for charge transport, charge selectivity and optimal device performance. I have categorized transparent semiconductors into two sub groups depending upon their role in a device. Electrodes, usually 200 to 500 nm thick, optimized for good transparency and transporting the charges to the external circuit. Here, the electrical conductivity in parallel direction to thin film, i.e bulk conductivity is important. And contacts, usually 5 to 50 nm thick, are optimized in case of solar cells for providing charge selectivity and asymmetry to manipulate the built in field inside the device for charge separation and collection. Whereas in Organic LEDs (OLEDs), contacts provide optimum energy level alignment at organic oxide interface for improved charge injections. For an optimal solar cell performance, transparent electrodes are designed with maximum transparency in the region of interest to maximize the light to pass through to the absorber layer for photo-generation, plus they are designed for minimum sheet resistance for efficient charge collection and transport. As such there is need for material with high conductivity and transparency. Doping ZnO with some common elements such as B, Al, Ga, In, Ge, Si, and F result in n-type doping with increase in carriers resulting in high conductivity electrode, with better or comparable opto-electronic properties compared to current industry-standard indium tin oxide (ITO). Furthermore, improvement in mobility due to improvement on crystallographic structure also provide alternative path for high conductivity ZnO TCOs. Implementing these two aspects, various studies were done on gallium doped zinc oxide (GZO) transparent electrode, a very promising indium free electrode. The dynamics of the superimposed RF and DC power sputtering was utilized to improve the microstructure during the thin films growth, resulting in GZO electrode with conductivity greater than 4000 S/cm and transparency greater than 90 %. Similarly, various studies on research and development of Indium Zinc Tin Oxide and Indium Zinc Oxide thin films which can be applied to flexible substrates for next generation solar cells application is presented. In these new TCO systems, understanding the role of crystallographic structure ranging from poly-crystalline to amorphous phase and the influence on the charge transport and optical transparency as well as important surface passivation and surface charge transport properties. Implementation of these electrode based on ZnO on opto-electronics devices such as OLED and OPV is complicated due to chemical interaction over time with the organic layer or with ambient. The problem of inefficient charge collection/injection due to poor understanding of interface and/or bulk property of oxide electrode exists at several oxide-organic interfaces. The surface conductivity, the work function, the formation of dipoles and the band-bending at the interfacial sites can positively or negatively impact the device performance. Detailed characterization of the surface composition both before and after various chemicals treatment of various oxide electrode can therefore provide insight into optimization of device performance. Some of the work related to controlling the interfacial chemistry associated with charge transport of transparent electrodes are discussed. Thus, the role of various pre-treatment on poly-crystalline GZO electrode and amorphous indium zinc oxide (IZO) electrode is compared and contrasted. From the study, we have found that removal of defects and self passivating defects caused by accumulation of hydroxides in the surface of both poly-crystalline GZO and amorphous IZO, are critical for improving the surface conductivity and charge transport. Further insight on how these insulating and self-passivating defects cause charge accumulation and recombination in an device is discussed. With recent rapid development of bulk-heterojunction organic photovoltaics active materials, devices employing ZnO and ZnO based electrode provide air stable and cost-competitive alternatives to traditional inorganic photovoltaics. The organic light emitting diodes (OLEDs) have already been commercialized, thus to follow in the footsteps of this technology, OPV devices need further improvement in power conversion efficiency and stable materials resulting in long device lifetimes. Use of low work function metals such as Ca/Al in standard geometry do provide good electrode for electron collection, but serious problems using low work-function metal electrodes originates from the formation of non-conductive metal oxide due to oxidation resulting in rapid device failure. Hence, using low work-function, air stable, conductive metal oxides such as ZnO as electrons collecting electrode and high work-function, air stable metals such as silver for harvesting holes, has been on the rise. Devices with degenerately doped ZnO functioning as transparent conductive electrode, or as charge selective layer in a polymer/fullerene based heterojunction, present useful device structures for investigating the functional mechanisms within OPV devices and a possible pathway towards improved air-stable high efficiency devices. Furthermore, analysis of the physical properties of the ZnO layers with varying thickness, crystallographic structure, surface chemistry and grain size deposited via various techniques such as atomic layer deposition, sputtering and solution-processed ZnO with their respective OPV device performance is discussed. We find similarity and differences in electrode property for good charge injection in OLEDs and good charge collection in OPV devices very insightful in understanding physics behind device failures and successes. In general, self-passivating surface of amorphous TCOs IZO, ZTO and IZTO forms insulating layer that hinders the charge collection. Similarly, we find modulation of the carrier concentration and the mobility in electron transport layer, namely zinc oxide thin films, very important for optimizing device performance.

Estudo de transistores de tunelamento induzido por efeito de campo (TFET) construídos em nanofio.

Esse trabalho de mestrado teve como estudo o transistor Túnel-FET (TFET) fabricado em estrutura de nanofio de silício. Este estudo foi feito de forma teórica (simulação numérica) e experimental. Foram estudadas as principais características digitais e analógicas do dispositivo e seu potencial para uso em circuitos integrados avançados para a próxima década. A análise foi feita através da extração experimental e estudo dos principais parâmetros do dispositivo, tais como inclinação de sublimiar, transcondutância (gm), condutância de saída (gd), ganho intrínseco de tensão (AV) e eficiência do transistor. As medidas experimentais foram comparadas com os resultados obtidos pela simulação. Através do uso de diferentes parâmetros de ajuste e modelos de simulação, justificou-se o comportamento do dispositivo observado experimentalmente. Durante a execução deste trabalho estudou-se a influência da escolha do material de fonte no desempenho do dispositivo, bem como o impacto do diâmetro do nanofio nos principais parâmetros analógicos do transistor. Os dispositivos compostos por fonte de SiGe apresentaram valores maiores de gm e gd do que aqueles compostos por fonte de silício. A diferença percentual entre os valores de transcondutância para os diferentes materiais de fonte variou de 43% a 96%, sendo dependente do método utilizado para comparação, e a diferença percentual entre os valores de condutância de saída variou de 38% a 91%. Observou-se também uma degradação no valor de AV com a redução do diâmetro do nanofio. O ganho calculado a partir das medidas experimentais para o dispositivo com diâmetro de 50 nm é aproximadamente 45% menor do que o correspondente ao diâmetro de 110 nm. Adicionalmente estudou-se o impacto do diâmetro considerando diferentes polarizações de porta (VG) e concluiu-se que os TFETs apresentam melhor desempenho para baixos valores de VG (houve uma redução de aproximadamente 88% no valor de AV com o aumento da tensão de porta de 1,25 V para 1,9 V). A sobreposição entre porta e fonte e o perfil de dopantes na junção de tunelamento também foram analisados a fim de compreender qual combinação dessas características resultariam em um melhor desempenho do dispositivo. Observou-se que os melhores resultados estavam associados a um alinhamento entre o eletrodo de porta e a junção entre fonte e canal e a um perfil abrupto de dopantes na junção. Por fim comparou-se a tecnologia MOS com o TFET, obtendo-se como resultado um maior valor de AV (maior do que 40 dB) para o TFET.

Caracterização elétrica de túnel-FET em estrutura de nanofio com fontes de SiGe e Ge em função da temperatura.

Este trabalho teve como objetivo estudar os transistores de tunelamento por efeito de campo em estruturas de nanofio (NW-TFET), sendo realizado através de analises com base em explicações teóricas, simulações numéricas e medidas experimentais. A fim de avaliar melhorar o desempenho do NW-TFET, este trabalho utilizou dispositivos com diferentes materiais de fonte, sendo eles: Si, liga SiGe e Ge, além da variação da espessura de HfO2 no material do dielétrico de porta. Com o auxílio de simulações numéricas foram obtidos os diagramas de bandas de energia dos dispositivos NW-TFET com fonte de Si0,73Ge0,27 e foi analisada a influência de cada um dos mecanismos de transporte de portadores para diversas condições de polarização, sendo observado a predominância da influência da recombinação e geração Shockley-Read-Hall (SRH) na corrente de desligamento, do tunelamento induzido por armadilhas (TAT) para baixos valores de tensões de porta (0,5V > VGS > 1,5V) e do tunelamento direto de banda para banda (BTBT) para maiores valores tensões de porta (VGS > 1,5V). A predominância de cada um desses mecanismos de transporte foi posteriormente comprovada com a utilização do método de Arrhenius, sendo este método adotado em todas as análises do trabalho. O comportamento relativamente constante da corrente dos NW-TFETs com a temperatura na região de BTBT tem chamado a atenção e por isso foi realizado o estudo dos parâmetros analógicos em função da temperatura. Este estudo foi realizado comparando a influência dos diferentes materiais de fonte. O uso de Ge na fonte, permitiu a melhora na corrente de tunelamento, devido à sua menor banda proibida, aumentando a corrente de funcionamento (ION) e a transcondutância do dispositivo. Porém, devido à forte dependência de BTBT com o campo elétrico, o uso de Ge na fonte resulta em uma maior degradação da condutância de saída. Entretanto, a redução da espessura de HfO2 no dielétrico de porta resultou no melhor acoplamento eletrostático, também aumentando a corrente de tunelamento, fazendo com que o dispositivo com fonte Ge e menor HfO2 apresentasse melhores resultados analógicos quando comparado ao puramente de Si. O uso de diferentes materiais durante o processo de fabricação induz ao aumento de defeitos nas interfaces do dispositivo. Ao longo deste trabalho foi realizado o estudo da influência da densidade de armadilhas de interface na corrente do dispositivo, demonstrando uma relação direta com o TAT e a formação de uma região de platô nas curvas de IDS x VGS, além de uma forte dependência com a temperatura, aumentando a degradação da corrente para temperaturas mais altas. Além disso, o uso de Ge introduziu maior número de impurezas no óxido, e através do estudo de ruído foi observado que o aumento na densidade de armadilhas no óxido resultou no aumento do ruído flicker em baixa frequência, que para o TFET, ocorre devido ao armadilhamento e desarmadilhamento de elétrons na região do óxido. E mais uma vez, o melhor acoplamento eletrostático devido a redução da espessura de HfO2, resultou na redução desse ruído tornando-se melhor quando comparado à um TFET puramente de Si. Neste trabalho foi proposto um modelo de ruído em baixa frequência para o NW-TFET baseado no modelo para MOSFET. Foram realizadas apenas algumas modificações, e assim, obtendo uma boa concordância com os resultados experimentais na região onde o BTBT é o mecanismo de condução predominante.

Effect of Cyclic Topology on Charge-Transfer Properties of Organic Molecular Semiconductors: The Case of Cycloparaphenylene Molecules

We have studied the role played by cyclic topology on charge-transfer properties of recently synthesized π -conjugated molecules, namely the set of [n]cycloparaphenylene compounds, with n the number of phenylene rings forming the curved nanoring. We estimate the charge-transfer rates for holes and electrons migration within the array of molecules in their crystalline state. The theoretical calculations suggest that increasing the size of the system would help to obtain higher hole and electron charge-transfer rates and that these materials might show an ambipolar behavior in real samples, independently of the different mode of packing followed by the [6]cycloparaphenylene and [12]cycloparaphenylene cases studied.

Morphology Change of C60 Islands on Organic Crystals Observed by Atomic Force Microscopy

Organic-organic heterojunctions are nowadays highly regarded materials for light-emitting diodes, field-effect transistors, and photovoltaic cells with the prospect of designing low-cost, flexible, and efficient electronic devices.1-3 However, the key parameter of optimized heterojunctions relies on the choice of the molecular compounds as well as on the morphology of the organic-organic interface,4 which thus requires fundamental studies. In this work, we investigated the deposition of C60 molecules at room temperature on an organic layer compound, the salt bis(benzylammonium)bis(oxalato)cupurate(II), by means of noncontact atomic force microscopy. Three-dimensional molecular islands of C60 having either triangular or hexagonal shapes are formed on the substrate following a "Volmer-Weber" type of growth. We demonstrate the dynamical reshaping of those C60 nanostructures under the local action of the AFM tip at room temperature. The dissipated energy is about 75 meV and can be interpreted as the activation energy required for this migration process.

Fundamentals of junction transistor physics /

"August 30, 1955"

General Electric transistor manual.

Cover title: Transistor manual, including tunnel diodes; specifications, applications, circuits.

G E transistor manual.

Cover title: Transistor manual, including signal diodes; applications, circuits, specifications.

A reverse-bias safe operating area transistor tester /

Includes bibliographical references (p. 14).

Operator, organizational, DS, GS, and depot maintenance manual : test set, transistor TS-1836B/U.

"October 1968."