A scalable packet sorting circuit for high-speed WFQ packet scheduling

A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.

Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality

Dynamic power consumption is very dependent on interconnect, so clever mapping of digital signal processing algorithms to parallelised realisations with data locality is vital. This is a particular problem for fast algorithm implementations where typically, designers will have sacrificed circuit structure for efficiency in software implementation. This study outlines an approach for reducing the dynamic power consumption of a class of fast algorithms by minimising the index space separation; this allows the generation of field programmable gate array (FPGA) implementations with reduced power consumption. It is shown how a 50% reduction in relative index space separation results in a measured power gain of 36 and 37% over a Cooley-Tukey Fast Fourier Transform (FFT)-based solution for both actual power measurements for a Xilinx Virtex-II FPGA implementation and circuit measurements for a Xilinx Virtex-5 implementation. The authors show the generality of the approach by applying it to a number of other fast algorithms namely the discrete cosine, the discrete Hartley and the Walsh-Hadamard transforms.

Fully hardware based WFQ architecture for high-speed QoS packet scheduling

A full hardware implementation of a Weighted Fair Queuing (WFQ) packet scheduler is proposed. The circuit architecture presented has been implemented using Altera Stratix II FPGA technology, utilizing RLDII and QDRII memory components. The circuit can provide fine granularity Quality of Service (QoS) support at a line throughput rate of 12.8Gb/s in its current implementation. The authors suggest that, due to the flexible and scalable modular circuit design approach used, the current circuit architecture can be targeted for a full ASIC implementation to deliver 50 Gb/s throughput. The circuit itself comprises three main components; a WFQ algorithm computation circuit, a tag/time-stamp sort and retrieval circuit, and a high throughput shared buffer. The circuit targets the support of emerging wireline and wireless network nodes that focus on Service Level Agreements (SLA's) and Quality of Experience.

The impact of biomarkers in multivariate algorithms for bladder cancer diagnosis in patients with hematuria

BACKGROUND: We appraised 23 biomarkers previously associated with urothelial cancer in a case-control study. Our aim was to determine whether single biomarkers and/or multivariate algorithms significantly improved on the predictive power of an algorithm based on demographics for prediction of urothelial cancer in patients presenting with hematuria. METHODS: Twenty-two biomarkers in urine and carcinoembryonic antigen (CEA) in serum were evaluated using enzyme-linked immunosorbent assays (ELISAs) and biochip array technology in 2 patient cohorts: 80 patients with urothelial cancer, and 77 controls with confounding pathologies. We used Forward Wald binary logistic regression analyses to create algorithms based on demographic variables designated prior predicted probability (PPP) and multivariate algorithms, which included PPP as a single variable. Areas under the curve (AUC) were determined after receiver-operator characteristic (ROC) analysis for single biomarkers and algorithms. RESULTS: After univariate analysis, 9 biomarkers were differentially expressed (t test; P