Multi-Tone Testing of Linear and Nonlinear Analog Circuits using Polynomial Coefficients

A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies in addition to DC. Classification or Cur is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. This testing method requires no design for test hardware as might be added to the circuit fly some other methods. The proposed method is illustrated for a benchmark elliptic filter. It is shown to uncover several parametric faults causing deviations as small as 5% from the nominal values.

Slim P‐E hysteresis loop and anomalous dielectric response in sol-gel derived antiferroelectric PbZrO3 thin films

Sol-gel derived PbZrO3 (PZ) thin films have been deposited on Pt(111)/Ti/SiO2/Si substrate and according to the pseudotetragonal symmetry of PZ, the relatively preferred (110)t oriented phase formation has been noticed. The room temperature P‐E hysteresis loops have been observed to be slim by nature. The slim hysteresis loops are attributed to the [110]t directional antiparallel lattice motion of Pb ions and by the directionality of the applied electric field. Pure PZ formation has been characterized by the dielectric phase transition at 235 °C and antiferroelectric P‐E hysteresis loops at room temperature. Dielectric response has been characterized within a frequency domain of 100 Hz–1 MHz at various temperatures ranging from 40 to 350 °C. Though frequency dispersion of dielectric behaves like a Maxwell–Wagner type of relaxation, ω2 dependency of ac conductivity indicates that there must be G‐C equivalent circuit dominance at high frequency. The presence of trap charges in PZ has been determined by Arrhenius plots of ac conductivity. The temperature dependent n (calculated from the universal power law of ac conductivity) values indicate an anomalous behavior of the trapped charges. This anomaly has been explained by strongly and weakly correlated potential wells of trapped charges and their behavior on thermal activation. The dominance of circuit∕circuits resembling Maxwell–Wagner type has been investigated by logarithmic Nyquist plots at various temperatures and it has been justified that the dielectric dispersion is not from the actual Maxwell–Wagner-type response.

Process variability-aware statistical hybrid modeling of dynamic power dissipation in 65 nm CMOS designs

A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in process parameters to variations in dynamic power of a digital circuit. The dynamic power of a 2-input NAND gate is characterized by mixed-mode simulations, to be used as a library element for 65mn gate length technology. The proposed methodology is demonstrated with a multiplier circuit built using the NAND gate library, by characterizing its dynamic power through Monte Carlo analysis. The statistical technique of Response. Surface Methodology (RSM) using Design of Experiments (DOE) and Least Squares Method (LSM), are employed to generate a "hybrid model" for gate power to account for simultaneous variations in multiple process parameters. We demonstrate that our hybrid model based statistical design approach results in considerable savings in the power budget of low power CMOS designs with an error of less than 1%, with significant reductions in uncertainty by atleast 6X on a normalized basis, against worst case design.

Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits

In this paper, the effects of energy quantization on different single-electron transistor (SET) circuits (logic inverter, current-biased circuits, and hybrid MOS-SET circuits) are analyzed through analytical modeling and Monte Carlo simulations. It is shown that energy quantizationmainly increases the Coulomb blockade area and Coulomb blockade oscillation periodicity, and thus, affects the SET circuit performance. A new model for the noise margin of the SET inverter is proposed, which includes the energy quantization effects. Using the noise margin as a metric, the robustness of the SET inverter is studied against the effects of energy quantization. An analytical expression is developed, which explicitly defines the maximum energy quantization (termed as ``quantization threshold'') that an SET inverter can withstand before its noise margin falls below a specified tolerance level. The effects of energy quantization are further studiedfor the current-biased negative differential resistance (NDR) circuitand hybrid SETMOS circuit. A new model for the conductance of NDR characteristics is also formulated that explains the energy quantization effects.

Linear transconductor with flipped voltage follower in 130 nm CMOS

This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit.

Rendering stiffer walls: a hybrid haptic system using continuous and discrete time feedback

Instability in conventional haptic rendering destroys the perception of rigid objects in virtual environments. Inherent limitations in the conventional haptic loop restrict the maximum stiffness that can be rendered. In this paper we present a method to render virtual walls that are much stiffer than those achieved by conventional techniques. By removing the conventional digital haptic loop and replacing it with a part-continuous and part-discrete time hybrid haptic loop, we were able to render stiffer walls. The control loop is implemented as a combinational logic circuit on an field-programmable gate array. We compared the performance of the conventional haptic loop and our hybrid haptic loop on the same haptic device, and present mathematical analysis to show the limit of stability of our device. Our hybrid method removes the computer-intensive haptic loop from the CPU-this can free a significant amount of resources that can be used for other purposes such as graphical rendering and physics modeling. It is our hope that, in the future, similar designs will lead to a haptics processing unit (HPU).

A simple analog controller for single-phase half-bridge rectifier and its application to transformerless UPS

A simple, low-cost, constant frequency, analog controller is proposed for the front-end half-bridge rectifier of a single-phase transformerless UPS system to maintain near unity power factor at the input and zero dc-offset voltage at the output. The controller generates the required gating pulses by comparing the input current with a periodic, bipolar, linear carrier without sensing the input voltage. Two voltage controllers and a single integrator with reset are used to generate the required carrier. All the necessary control operations can be performed without using any PLL, multiplier and/or divider. The controller can be fabricated as a single integrated circuit. The control concept is validated through simulation and also experimentally on an 800W half-bridge rectifier. Experimental results are presented for ac-dc application, and also for ac-dc-ac UPS application with both sinusoidal and nonlinear loads. The simulation and experimental results agree well.

A Proportional plus Multiresonant Controller for Three-Phase Four-Wire High-Frequency Link Inverter

A new solution for unbalanced and nonlinear loads in terms of power circuit topology and controller structure is proposed in this paper. A three-phase four-wire high-frequency ac-link inverter is adopted to cater to such loads. Use of high-frequency transformer results in compact and light-weight systems. The fourth wire is taken out from the midpoint of the isolation transformer in order to avoid the necessity of an extra leg. This makes the converter suitable for unbalanced loads and eliminates the requirements of bulky capacitor in half-bridge inverter. The closed-loop control is carried out in stationary reference frame using proportional + multiresonant controller (three separate resonant controller for fundamental, fifth and seventh harmonic components). The limitations on improving steady-state response of harmonic resonance controllers is investigated and mitigated using a lead-lag compensator. The proposed voltage controller is used along with an inner current loop to ensure excellent performance of the power converter. Simulation studies and experimental results with 1 kVA prototype under nonlinear and unbalanced loading conditions validate the proposed scheme.

Asymmetric cross-coupled differential pair configuration to realize neuron activation function and its derivative

In this brief, we present a new circuit technique to generate the sigmoid neuron activation function (NAF) and its derivative (DNAF). The circuit makes use of transistor asymmetry in cross-coupled differential pair to obtain the derivative. The asymmetry is introduced through external control signal, as and when required. This results in the efficient utilization of the hard-ware by realizing NAF and DNAF using the same building blocks. The operation of the circuit is presented in the subthreshold region for ultra low-power applications. The proposed circuit has been experimentally prototyped and characterized as a proof of concept on the 1.5-mum AMI technology.

Design of a compact wideband bandpass filter

This article presents the analysis and design of a compact multi-layer layer, high selectivity wideband bandpass filter using stub loaded and `U' shaped resonators over a slotted bottom ground plane. While the resonators with folded open circuit stub loadings create the desired bandpass characteristics. the IT shaped resonators reduce the size of filter. The slotted bottom ground plane is used to enhance the coupling to achieve the desired bandwidth. The proposed filter has been analyzed using circuit model, and the results were verified through full wave simulations and measurements. The fabricated filter is compact and measures a size of 18 mm x 25 mm x 1.6 MM. (C) 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 1387-1389, 2010: Published online in Wiley InterScience (www.interscience.wiley.com).

A hybrid computer for X-ray crystallography

A hybrid computer for structure factor calculations in X-ray crystallography is described. The computer can calculate three-dimensional structure factors of up to 24 atoms in a single run and can generate the scatter functions of well over 100 atoms using Vand et al., or Forsyth and Wells approximations. The computer is essentially a digital computer with analog function generators, thus combining to advantage the economic data storage of digital systems and simple computing circuitry of analog systems. The digital part serially selects the data, computes and feeds the arguments into specially developed high precision digital-analog function generators, the outputs of which being d.c. voltages, are further processed by analog circuits and finally the sequential adder, which employs a novel digital voltmeter circuit, converts them back into digital form and accumulates them in a dekatron counter which displays the final result. The computer is also capable of carrying out 1-, 2-, or 3-dimensional Fourier summation, although in this case, the lack of sufficient storage space for the large number of coefficients involved, is a serious limitation at present.

A Study of Practical Biological Phantoms with Simple Instrumentation for Electrical Impedance Tomography (EIT)

16-electrode phantoms are developed and studied with a simple instrumentation developed for Electrical Impedance Tomography. An analog instrumentation is developed with a sinusoidal current generator and signal conditioner circuit. Current generator is developed withmodified Howland constant current source fed by a voltage controlled oscillator and the signal conditioner circuit consisting of an instrumentation amplifier and a narrow band pass filter. Electronic hardware is connected to the electrodes through a DIP switch based multiplexer module. Phantoms with different electrode size and position are developed and the EIT forward problem is studied using the forward solver. A low frequency low magnitude sinusoidal current is injected to the surface electrodes surrounding the phantom boundary and the differential potential is measured by a digital multimeter. Comparing measured potential with the simulated data it is intended to reduce the measurement error and an optimum phantom geometry is suggested. Result shows that the common mode electrode reduces the common mode error of the EIT electronics and reduces the error potential in the measured data. Differential potential is reduced up to 67 mV at the voltage electrode pair opposite to the current electrodes. Offset potential is measured and subtracted from the measured data for further correction. It is noticed that the potential data pattern depends on the electrode width and the optimum electrode width is suggested. It is also observed that measured potential becomes acceptable with a 20 mm solution column above and below the electrode array level.

Analysis of Ridge-Loaded Folded-Waveguide Slow-Wave Structures for Broadband Traveling-Wave Tubes

An E-plane serpentine folded-waveguide slow-wave structure with ridge loading on one of its broad walls is proposed for broadband traveling-wave tubes (TWTs) and studied using a simple quasi-transverse-electromagnetic analysis for the dispersion and interaction impedance characteristics, including the effects of the beam-hole discontinuity. The results are validated against cold test measurements, an approximate transmission-line parametric analysis, an equivalent circuit analysis, and 3-D electromagnetic modeling using CST Microwave Studio. The effect of the structure parameters on widening the bandwidth of a TWT is also studied.

A Computationally Efficient Generalized Poisson Solution for Independent Double-Gate Transistors

Previous techniques used for solving the 1-D Poisson equation ( PE) rigorously for long-channel asymmetric and independent double-gate (IDG) transistors result in potential models that involve multiple intercoupled implicit equations. As these equations need to be solved self-consistently, such potential models are clearly inefficient for compact modeling. This paper reports a different rigorous technique for solving the same PE by which one can obtain the potential profile of a generalized IDG transistor that involves a single implicit equation. The proposed Poisson solution is shown to be computationally more efficient for circuit simulation than the previous solutions.

Diketopyrrolopyrrole-Based Donor-Acceptor Copolymers as Organic Sensitizers for Dye Sensitized Solar Cells

In this work diketopyrrolopyrrole based copolymers (PDPP-BBT and TDPP-BBT) containing a donor-acceptor structural unit have been explored as organic Sensitizers for quasi-solid state dye Sensitized solar cells. Polymer-sensitized solar cells (PSSC) fabricated utilizing PDPP-BBT and TDPP-BBT as the active layer resulted in a typical power conversion efficiency of 1.43% and 2.41%, respectively. The power conversion efficiency of PSSCs based on TDPP-BBT With use of TiCl4-modified TiO2 photoanode was about 3.06%, attributed to the reduced back recombination reaction and more charge carriers in the external Circuit.